Function: `verilog-auto-assign-modport`

verilog-auto-assign-modport is a byte-compiled function defined in verilog-mode.el.gz.

Signature

(verilog-auto-assign-modport)

Documentation

Expand AUTOASSIGNMODPORT statements, as part of M-x verilog-auto (verilog-auto).

Take input/output/inout statements from the specified interface and modport and use to build assignments into the modport, for making verification modules that connect to UVM interfaces.

The first parameter is the name of an interface.

The second parameter is a regexp of modports to read from in
that interface.

The third parameter is the instance name to use to dot reference into.

The optional fourth parameter is a regular expression, and only
signals matching the regular expression will be included.

The optional fifth parameter is a prefix to add to the signals.

Limitations:

Interface names must be resolvable to filenames. See verilog-auto-inst.

Inouts are not supported, as assignments must be unidirectional.

  If a signal is part of the interface header and in both a
  modport and the interface itself, it will not be listed. (As
  this would result in a syntax error when the connections are
  made.)

See the example in verilog-auto-inout-modport.

Source Code

;; Defined in /usr/src/emacs/lisp/progmodes/verilog-mode.el.gz
(defun verilog-auto-assign-modport ()
  "Expand AUTOASSIGNMODPORT statements, as part of \\[verilog-auto].
Take input/output/inout statements from the specified interface
and modport and use to build assignments into the modport, for
making verification modules that connect to UVM interfaces.

  The first parameter is the name of an interface.

  The second parameter is a regexp of modports to read from in
  that interface.

  The third parameter is the instance name to use to dot reference into.

  The optional fourth parameter is a regular expression, and only
  signals matching the regular expression will be included.

  The optional fifth parameter is a prefix to add to the signals.

Limitations:

  Interface names must be resolvable to filenames.  See `verilog-auto-inst'.

  Inouts are not supported, as assignments must be unidirectional.

  If a signal is part of the interface header and in both a
  modport and the interface itself, it will not be listed.  (As
  this would result in a syntax error when the connections are
  made.)

See the example in `verilog-auto-inout-modport'."
  (save-excursion
    (let* ((params (verilog-read-auto-params 3 5))
	   (submod (nth 0 params))
	   (modport-re (nth 1 params))
	   (inst-name (nth 2 params))
	   (regexp (nth 3 params))
           (prefix (nth 4 params))
           ;; direction-re  ; direction argument not supported until requested
           submodi)
      ;; Lookup position, etc of co-module
      ;; Note this may raise an error
      (when (setq submodi (verilog-modi-lookup submod t))
	(let* ((indent-pt (current-indentation))
	       (submoddecls (verilog-modi-get-decls submodi))
	       (submodportdecls (verilog-modi-modport-lookup submodi modport-re))
               (sig-list-i (verilog-signals-in  ; Decls doesn't have data types, must resolve
			    (verilog-decls-get-vars submoddecls)
			    (verilog-signals-not-in
			     (verilog-decls-get-inputs submodportdecls)
			     (verilog-decls-get-ports submoddecls))))
               (sig-list-o (verilog-signals-in  ; Decls doesn't have data types, must resolve
			    (verilog-decls-get-vars submoddecls)
			    (verilog-signals-not-in
			     (verilog-decls-get-outputs submodportdecls)
			     (verilog-decls-get-ports submoddecls)))))
	  (forward-line 1)
	  (setq sig-list-i  (verilog-signals-edit-wire-reg
			     (verilog-signals-matching-dir-re
			      (verilog-signals-matching-regexp sig-list-i regexp)
                             "input" nil)) ;; direction-re
		sig-list-o  (verilog-signals-edit-wire-reg
			     (verilog-signals-matching-dir-re
			      (verilog-signals-matching-regexp sig-list-o regexp)
                             "output" nil))) ;; direction-re
	  (setq sig-list-i (sort (copy-alist sig-list-i) #'verilog-signals-sort-compare))
	  (setq sig-list-o (sort (copy-alist sig-list-o) #'verilog-signals-sort-compare))
	  (when (or sig-list-i sig-list-o)
	    (verilog-insert-indent "// Beginning of automatic assignments from modport\n")
	    ;; Don't sort them so an upper AUTOINST will match the main module
	    (let ((sigs sig-list-o))
	      (while sigs
                (verilog-insert-indent "assign "
                                       (concat prefix (verilog-sig-name (car sigs)))
                                       " = " inst-name
                                       "." (verilog-sig-name (car sigs)) ";\n")
		(setq sigs (cdr sigs))))
	    (let ((sigs sig-list-i))
	      (while sigs
                (verilog-insert-indent "assign " inst-name
                                       "." (verilog-sig-name (car sigs))
                                       " = "
                                       (concat prefix (verilog-sig-name (car sigs)))
                                       ";\n")
		(setq sigs (cdr sigs))))
	    (verilog-insert-indent "// End of automatics\n")))))))

Function: verilog-auto-assign-modport

Signature

Documentation

Source Code

Function: `verilog-auto-assign-modport`