Function: verilog-auto-inst-param

verilog-auto-inst-param is a byte-compiled function defined in verilog-mode.el.gz.

Signature

(verilog-auto-inst-param)

Documentation

Expand AUTOINSTPARAM statements, as part of M-x verilog-auto (verilog-auto).

Replace the parameter connections to an instantiation with ones automatically derived from the module header of the instantiated netlist.

You may also provide an optional regular expression, in which case only parameters matching the regular expression will be included, or excluded if the regexp begins with ?! (question-mark exclamation-mark).

See M-x verilog-auto-inst (verilog-auto-inst) for limitations, and templates to customize the output.

For example, first take the submodule InstModule.v:

        module InstModule (o,i);
           parameter PAR;
        endmodule

This is then used in an upper level module:

        module ExampInstParam (o,i);
           parameter PAR;
           InstModule #(/*AUTOINSTPARAM*/)
                instName (/*AUTOINST*/);
        endmodule

Typing M-x verilog-auto (verilog-auto) will make this into:

        module ExampInstParam (o,i);
           parameter PAR;
           InstModule #(/*AUTOINSTPARAM*/
                        // Parameters
                        .PAR (PAR))
                instName (/*AUTOINST*/);
        endmodule

Where the list of parameter connections come from the inst module.

Templates:

  You can customize the parameter connections using AUTO_TEMPLATEs,
  just as you would with M-x verilog-auto-inst (verilog-auto-inst).

Source Code

;; Defined in /usr/src/emacs/lisp/progmodes/verilog-mode.el.gz
(defun verilog-auto-inst-param ()
  "Expand AUTOINSTPARAM statements, as part of \\[verilog-auto].
Replace the parameter connections to an instantiation with ones
automatically derived from the module header of the instantiated netlist.

You may also provide an optional regular expression, in which
case only parameters matching the regular expression will be
included, or excluded if the regexp begins with ?! (question-mark
exclamation-mark).

See \\[verilog-auto-inst] for limitations, and templates to customize the
output.

For example, first take the submodule InstModule.v:

        module InstModule (o,i);
           parameter PAR;
        endmodule

This is then used in an upper level module:

        module ExampInstParam (o,i);
           parameter PAR;
           InstModule #(/*AUTOINSTPARAM*/)
                instName (/*AUTOINST*/);
        endmodule

Typing \\[verilog-auto] will make this into:

        module ExampInstParam (o,i);
           parameter PAR;
           InstModule #(/*AUTOINSTPARAM*/
                        // Parameters
                        .PAR    (PAR))
                instName (/*AUTOINST*/);
        endmodule

Where the list of parameter connections come from the inst module.

Templates:

  You can customize the parameter connections using AUTO_TEMPLATEs,
  just as you would with \\[verilog-auto-inst]."
  (save-excursion
    ;; Find beginning
    (let* ((params (verilog-read-auto-params 0 1))
           (regexp (nth 0 params))
           (pt (point))
	   (indent-pt (save-excursion (verilog-backward-open-paren)
				      (1+ (current-column))))
	   (verilog-auto-inst-column (max verilog-auto-inst-column
					  (+ 16 (* 8 (/ (+ indent-pt 7) 8)))))
           (verilog-auto-inst-first-any t)
	   (modi (verilog-modi-current))
	   (moddecls (verilog-modi-get-decls modi))
	   submod submodi submoddecls
           inst skip-pins tpl-list tpl-num)
      ;; Find module name that is instantiated
      (setq submod (save-excursion
		     ;; Get to the point where AUTOINST normally is to read the module
		     (verilog-re-search-forward-quick "[(;]" nil nil)
		     (verilog-read-inst-module))
	    inst   (save-excursion
		     ;; Get to the point where AUTOINST normally is to read the module
		     (verilog-re-search-forward-quick "[(;]" nil nil)
		     (verilog-read-inst-name))
	    vl-cell-type submod
	    vl-cell-name inst
	    skip-pins (aref (verilog-read-inst-pins) 0))

      ;; Parse any AUTO_LISP() before here
      (verilog-read-auto-lisp (point-min) pt)

      ;; Lookup position, etc of submodule
      ;; Note this may raise an error
      (when (setq submodi (verilog-modi-lookup submod t))
	(setq submoddecls (verilog-modi-get-decls submodi))
	;; If there's a number in the instantiation, it may be an argument to the
	;; automatic variable instantiation program.
	(let* ((tpl-info (verilog-read-auto-template submod))
	       (tpl-regexp (aref tpl-info 0)))
	  (setq tpl-num (if (verilog-string-match-fold tpl-regexp inst)
			    (match-string 1 inst)
			  "")
		tpl-list (aref tpl-info 1)))
	;; Find submodule's signals and dump
	(let ((sig-list (verilog-signals-not-in
			 (verilog-decls-get-gparams submoddecls)
			 skip-pins))
	      (vl-dir "parameter"))
          (when regexp
            (setq sig-list (verilog-signals-matching-regexp sig-list regexp)))
	  (when sig-list
            ;; Note these are searched for in verilog-read-sub-decls.
            (verilog-auto-inst-port-list "// Parameters\n"
                                         sig-list indent-pt moddecls
					 tpl-list tpl-num nil nil)))
	;; Kill extra semi
	(save-excursion
          (cond ((not verilog-auto-inst-first-any)
		 (re-search-backward "," pt t)
		 (delete-char 1)
		 (insert ")")
                 (search-forward "\n")  ; Added by inst-port
		 (delete-char -1)
                 (if (search-forward ")" nil t)  ; From user, moved up a line
		     (delete-char -1)))))))))