Function: verilog-auto-reg

verilog-auto-reg is a byte-compiled function defined in verilog-mode.el.gz.

Signature

(verilog-auto-reg)

Documentation

Expand AUTOREG statements, as part of M-x verilog-auto (verilog-auto).

Make reg statements for any output that isn't already declared, and isn't a wire output from a block. verilog-auto-wire-type may be used to change the datatype of the declarations.

Limitations:
  This ONLY detects outputs of AUTOINSTants (see verilog-read-sub-decls).

  This does NOT work on memories, declare those yourself.

An example:

        module ExampReg (o,i);
           output o;
           input i;
           /*AUTOREG*/
           always o = i;
        endmodule

Typing M-x verilog-auto (verilog-auto) will make this into:

        module ExampReg (o,i);
           output o;
           input i;
           /*AUTOREG*/
           // Beginning of automatic regs
           reg o;
           // End of automatics
           always o = i;
        endmodule

Source Code

;; Defined in /usr/src/emacs/lisp/progmodes/verilog-mode.el.gz
(defun verilog-auto-reg ()
  "Expand AUTOREG statements, as part of \\[verilog-auto].
Make reg statements for any output that isn't already declared,
and isn't a wire output from a block.  `verilog-auto-wire-type'
may be used to change the datatype of the declarations.

Limitations:
  This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').

  This does NOT work on memories, declare those yourself.

An example:

        module ExampReg (o,i);
           output o;
           input i;
           /*AUTOREG*/
           always o = i;
        endmodule

Typing \\[verilog-auto] will make this into:

        module ExampReg (o,i);
           output o;
           input i;
           /*AUTOREG*/
           // Beginning of automatic regs
           reg          o;
           // End of automatics
           always o = i;
        endmodule"
  (save-excursion
    ;; Point must be at insertion point.
    (let* ((indent-pt (current-indentation))
	   (modi (verilog-modi-current))
	   (moddecls (verilog-modi-get-decls modi))
	   (modsubdecls (verilog-modi-get-sub-decls modi))
	   (sig-list (verilog-signals-not-in
		      (verilog-decls-get-outputs moddecls)
                      (append (verilog-signals-with  ; ignore typed signals
			       'verilog-sig-type
			       (verilog-decls-get-outputs moddecls))
			      (verilog-decls-get-vars moddecls)
			      (verilog-decls-get-assigns moddecls)
			      (verilog-decls-get-consts moddecls)
			      (verilog-decls-get-gparams moddecls)
			      (verilog-subdecls-get-interfaced modsubdecls)
			      (verilog-subdecls-get-outputs modsubdecls)
			      (verilog-subdecls-get-inouts modsubdecls)))))
      (when sig-list
	(verilog-forward-or-insert-line)
	(verilog-insert-indent "// Beginning of automatic regs (for this module's undeclared outputs)\n")
	(verilog-insert-definition modi sig-list "reg" indent-pt nil)
	(verilog-insert-indent "// End of automatics\n")))))