Function: verilog-auto-wire

verilog-auto-wire is a byte-compiled function defined in verilog-mode.el.gz.

Signature

(verilog-auto-wire)

Documentation

Expand AUTOWIRE statements, as part of M-x verilog-auto (verilog-auto).

Make wire statements for instantiations outputs that aren't already declared. verilog-auto-wire-type may be used to change the datatype of the declarations.

Limitations:
  This ONLY detects outputs of AUTOINSTants (see verilog-read-sub-decls),
  and all buses must have widths, such as those from AUTOINST, or using []
  in AUTO_TEMPLATEs.

  This does NOT work on memories or SystemVerilog .name connections,
  declare those yourself.

  Verilog mode will add "Couldn't Merge" comments to signals it cannot
  determine how to bus together. This occurs when you have ports with
  non-numeric or non-sequential bus subscripts. If Verilog mode
  mis-guessed, you'll have to declare them yourself.

An example (see verilog-auto-inst for what else is going on here):

        module ExampWire (i);
           input i;
           /*AUTOWIRE*/
           InstModule instName
             (/*AUTOINST*/);
        endmodule

Typing M-x verilog-auto (verilog-auto) will make this into:

        module ExampWire (i);
           input i;
           /*AUTOWIRE*/
           // Beginning of automatic wires
           wire [31:0] o; // From instName of InstModule.v
           // End of automatics
           InstModule instName
             (/*AUTOINST*/
              // Outputs
              .o (o[31:0]),
              // Inputs
              .i (i));
           wire o = | ov;
        endmodule

Source Code

;; Defined in /usr/src/emacs/lisp/progmodes/verilog-mode.el.gz
(defun verilog-auto-wire ()
  "Expand AUTOWIRE statements, as part of \\[verilog-auto].
Make wire statements for instantiations outputs that aren't
already declared.  `verilog-auto-wire-type' may be used to change
the datatype of the declarations.

Limitations:
  This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls'),
  and all buses must have widths, such as those from AUTOINST, or using []
  in AUTO_TEMPLATEs.

  This does NOT work on memories or SystemVerilog .name connections,
  declare those yourself.

  Verilog mode will add \"Couldn't Merge\" comments to signals it cannot
  determine how to bus together.  This occurs when you have ports with
  non-numeric or non-sequential bus subscripts.  If Verilog mode
  mis-guessed, you'll have to declare them yourself.

An example (see `verilog-auto-inst' for what else is going on here):

        module ExampWire (i);
           input i;
           /*AUTOWIRE*/
           InstModule instName
             (/*AUTOINST*/);
        endmodule

Typing \\[verilog-auto] will make this into:

        module ExampWire (i);
           input i;
           /*AUTOWIRE*/
           // Beginning of automatic wires
           wire [31:0]  o;      // From instName of InstModule.v
           // End of automatics
           InstModule instName
             (/*AUTOINST*/
              // Outputs
              .o        (o[31:0]),
              // Inputs
              .i        (i));
           wire o = | ov;
        endmodule"
  (save-excursion
    ;; Point must be at insertion point.
    (let* ((indent-pt (current-indentation))
	   (modi (verilog-modi-current))
	   (moddecls (verilog-modi-get-decls modi))
	   (modsubdecls (verilog-modi-get-sub-decls modi))
	   (sig-list (verilog-signals-combine-bus
		      (verilog-signals-not-in
		       (append (verilog-subdecls-get-outputs modsubdecls)
			       (verilog-subdecls-get-inouts modsubdecls))
		       (verilog-decls-get-signals moddecls)))))
      (when sig-list
	(verilog-forward-or-insert-line)
	(verilog-insert-indent "// Beginning of automatic wires (for undeclared instantiated-module outputs)\n")
	(verilog-insert-definition modi sig-list "wire" indent-pt nil)
	(verilog-insert-indent "// End of automatics\n")
	;; We used to optionally call verilog-pretty-declarations and
	;; verilog-pretty-expr here, but it's too slow on huge modules,
	;; plus makes everyone's module change. Finally those call
	;; syntax-ppss which is broken when change hooks are disabled.
	))))