Variable: verilog-auto-simplify-expressions

verilog-auto-simplify-expressions is a customizable variable defined in verilog-mode.el.gz.

Value

t

Documentation

Non-nil means AUTOs will simplify expressions when calculating bit ranges.

When nil, do not simply ranges, which may simplify the output, but may cause problems when there are multiple instantiations outputting to the same wire. To maintain compatibility with other sites, this should be set at the bottom of each Verilog file that requires it, rather than being set globally.

This variable was added, or its default value changed, in Emacs 27.1.

Source Code

;; Defined in /usr/src/emacs/lisp/progmodes/verilog-mode.el.gz
(defcustom verilog-auto-simplify-expressions t
  "Non-nil means AUTOs will simplify expressions when calculating bit ranges.
When nil, do not simply ranges, which may simplify the output,
but may cause problems when there are multiple instantiations
outputting to the same wire.  To maintain compatibility with
other sites, this should be set at the bottom of each Verilog
file that requires it, rather than being set globally."
  :version "27.1"
  :group 'verilog-mode-auto
  :type 'boolean)