Variable: verilog-project

verilog-project is a buffer-local variable defined in verilog-mode.el.gz.

Documentation

Default name of Project for Verilog header.

If set will become buffer local.

Source Code

;; Defined in /usr/src/emacs/lisp/progmodes/verilog-mode.el.gz
(defvar verilog-project nil
  "Default name of Project for Verilog header.
If set will become buffer local.")