Variable: verilog-template-map

verilog-template-map is a variable defined in verilog-mode.el.gz.

Value

/  verilog-sk-comment
:  verilog-sk-else-if
=  verilog-sk-inout
?  verilog-sk-if
A  verilog-sk-assign
D  verilog-sk-define-signal
F  verilog-sk-function
I  verilog-sk-input
O  verilog-sk-output
R  verilog-sk-reg
S  verilog-sk-state-machine
U  verilog-sk-uvm-component
W  verilog-sk-wire
a  verilog-sk-always
b  verilog-sk-begin
c  verilog-sk-case
f  verilog-sk-for
g  verilog-sk-generate
h  verilog-sk-header
i  verilog-sk-initial
j  verilog-sk-fork
m  verilog-sk-module
o  verilog-sk-ovm-class
p  verilog-sk-primitive
r  verilog-sk-repeat
s  verilog-sk-specify
t  verilog-sk-task
u  verilog-sk-uvm-object
w  verilog-sk-while
x  verilog-sk-casex
z  verilog-sk-casez

Documentation

Keymap used in Verilog mode for smart template operations.

Source Code

;; Defined in /usr/src/emacs/lisp/progmodes/verilog-mode.el.gz
;;; Skeletons:
;;

(defvar verilog-template-map
  (let ((map (make-sparse-keymap)))
    (define-key map "a" #'verilog-sk-always)
    (define-key map "b" #'verilog-sk-begin)
    (define-key map "c" #'verilog-sk-case)
    (define-key map "f" #'verilog-sk-for)
    (define-key map "g" #'verilog-sk-generate)
    (define-key map "h" #'verilog-sk-header)
    (define-key map "i" #'verilog-sk-initial)
    (define-key map "j" #'verilog-sk-fork)
    (define-key map "m" #'verilog-sk-module)
    (define-key map "o" #'verilog-sk-ovm-class)
    (define-key map "p" #'verilog-sk-primitive)
    (define-key map "r" #'verilog-sk-repeat)
    (define-key map "s" #'verilog-sk-specify)
    (define-key map "t" #'verilog-sk-task)
    (define-key map "u" #'verilog-sk-uvm-object)
    (define-key map "w" #'verilog-sk-while)
    (define-key map "x" #'verilog-sk-casex)
    (define-key map "z" #'verilog-sk-casez)
    (define-key map "?" #'verilog-sk-if)
    (define-key map ":" #'verilog-sk-else-if)
    (define-key map "/" #'verilog-sk-comment)
    (define-key map "A" #'verilog-sk-assign)
    (define-key map "F" #'verilog-sk-function)
    (define-key map "I" #'verilog-sk-input)
    (define-key map "O" #'verilog-sk-output)
    (define-key map "S" #'verilog-sk-state-machine)
    (define-key map "=" #'verilog-sk-inout)
    (define-key map "U" #'verilog-sk-uvm-component)
    (define-key map "W" #'verilog-sk-wire)
    (define-key map "R" #'verilog-sk-reg)
    (define-key map "D" #'verilog-sk-define-signal)
    map)
  "Keymap used in Verilog mode for smart template operations.")