Variable: vhdl-mode-map

'              vhdl-electric-quote
,              vhdl-electric-comma
-              vhdl-electric-dash
.              vhdl-electric-period
;              vhdl-electric-semicolon
C-M-\          indent-region
C-M-a          vhdl-backward-same-indent
C-M-b          vhdl-backward-sexp
C-M-e          vhdl-forward-same-indent
C-M-f          vhdl-forward-sexp
C-M-h          vhdl-mark-defun
C-M-i          insert-tab
C-M-q          vhdl-indent-sexp
C-M-u          vhdl-backward-up-list
C-c -          vhdl-comment-append-inline
C-c C-M-k      vhdl-make
C-c C-a C-a    vhdl-align-group
C-c C-a C-b    vhdl-align-buffer
C-c C-a C-c    vhdl-align-inline-comment-group
C-c C-a C-d    vhdl-align-declarations
C-c C-a C-g    vhdl-align-group
C-c C-a C-l    vhdl-align-list
C-c C-a M-a    vhdl-align-region
C-c C-a M-c    vhdl-align-inline-comment-region
C-c C-a TAB    vhdl-align-same-indent(var)/vhdl-align-same-indent(fun)
C-c C-b        vhdl-beautify-buffer
C-c C-c        vhdl-comment-uncomment-region
C-c C-f C-f    vhdl-fill-list
C-c C-f C-g    vhdl-fill-group
C-c C-f C-l    vhdl-fill-list
C-c C-f M-f    vhdl-fill-region
C-c C-f TAB    vhdl-fill-same-indent
C-c C-h        vhdl-doc-mode
C-c C-k        vhdl-compile
C-c C-l C-c    vhdl-comment-uncomment-line
C-c C-l C-g    goto-line
C-c C-l C-n    vhdl-line-transpose-next
C-c C-l C-o    vhdl-line-open
C-c C-l C-p    vhdl-line-transpose-previous
C-c C-l C-w    vhdl-line-kill
C-c C-l C-y    vhdl-line-yank
C-c C-l M-w    vhdl-line-copy
C-c C-l TAB    vhdl-line-expand
C-c C-p C-c    vhdl-port-paste-component
C-c C-p C-d    vhdl-duplicate-project
C-c C-p C-e    vhdl-port-paste-entity
C-c C-p C-f    vhdl-port-flatten
C-c C-p C-g    vhdl-port-paste-generic-map
C-c C-p C-r    vhdl-port-reverse-direction
C-c C-p C-s    vhdl-port-paste-signals
C-c C-p C-t    vhdl-port-paste-testbench
C-c C-p C-w    vhdl-port-copy
C-c C-p C-x    vhdl-export-project
C-c C-p C-z    vhdl-port-paste-initializations
C-c C-p M-c    vhdl-port-paste-constants
C-c C-p M-w    vhdl-port-copy
C-c C-p RET    vhdl-import-project
C-c C-p TAB    vhdl-port-paste-instance
C-c C-s C-b    vhdl-subprog-paste-body
C-c C-s C-c    vhdl-subprog-paste-call
C-c C-s C-d    vhdl-subprog-paste-declaration
C-c C-s C-f    vhdl-subprog-flatten
C-c C-s C-k    vhdl-set-compiler
C-c C-s C-p    vhdl-set-project
C-c C-s C-w    vhdl-subprog-copy
C-c C-s M-w    vhdl-subprog-copy
C-c C-t (      vhdl-template-paired-parens
C-c C-t C b    vhdl-template-block-configuration
C-c C-t C c    vhdl-template-component-conf
C-c C-t C d    vhdl-template-configuration-decl
C-c C-t C s    vhdl-template-configuration-spec
C-c C-t C-d F  vhdl-template-directive-synthesis-off
C-c C-t C-d N  vhdl-template-directive-synthesis-on
C-c C-t C-d f  vhdl-template-directive-translate-off
C-c C-t C-d n  vhdl-template-directive-translate-on
C-c C-t C-f    vhdl-template-footer
C-c C-t C-h    vhdl-template-header
C-c C-t C-p A  vhdl-template-package-std-logic-arith
C-c C-t C-p M  vhdl-template-package-std-logic-misc
C-c C-t C-p S  vhdl-template-package-std-logic-signed
C-c C-t C-p T  vhdl-template-package-std-logic-textio
C-c C-t C-p U  vhdl-template-package-std-logic-unsigned
C-c C-t C-p b  vhdl-template-package-numeric-bit
C-c C-t C-p n  vhdl-template-package-numeric-std
C-c C-t C-p s  vhdl-template-package-std-logic-1164
C-c C-t C-p t  vhdl-template-package-textio
C-c C-t C-q    vhdl-template-search-prompt
C-c C-t C-t    vhdl-template-insert-date
C-c C-t P b    vhdl-template-package-body
C-c C-t P d    vhdl-template-package-decl
C-c C-t RET    vhdl-template-modify
C-c C-t a d    vhdl-template-attribute-decl
C-c C-t a l    vhdl-template-alias
C-c C-t a r    vhdl-template-architecture
C-c C-t a s    vhdl-template-attribute-spec
C-c C-t a t    vhdl-template-assert
C-c C-t b l    vhdl-template-block
C-c C-t c a    vhdl-template-case-is
C-c C-t c d    vhdl-template-component-decl
C-c C-t c i    vhdl-template-component-inst
C-c C-t c o    vhdl-template-constant
C-c C-t c s    vhdl-template-conditional-signal-asst
C-c C-t c t    vhdl-template-context
C-c C-t d i    vhdl-template-disconnect
C-c C-t e i    vhdl-template-elsif
C-c C-t e l    vhdl-template-else
C-c C-t e n    vhdl-template-entity
C-c C-t e x    vhdl-template-exit
C-c C-t f b    vhdl-template-function-body
C-c C-t f d    vhdl-template-function-decl
C-c C-t f g    vhdl-template-for-generate
C-c C-t f i    vhdl-template-file
C-c C-t f l    vhdl-template-for-loop
C-c C-t g d    vhdl-template-group-decl
C-c C-t g e    vhdl-template-generic
C-c C-t g t    vhdl-template-group-template
C-c C-t i g    vhdl-template-if-generate
C-c C-t i t    vhdl-template-if-then
C-c C-t l i    vhdl-template-library
C-c C-t l o    vhdl-template-bare-loop
C-c C-t m a    vhdl-template-map(var)/vhdl-template-map(fun)
C-c C-t n e    vhdl-template-next
C-c C-t o t    vhdl-template-others
C-c C-t p b    vhdl-template-procedure-body
C-c C-t p c    vhdl-template-process-comb
C-c C-t p d    vhdl-template-procedure-decl
C-c C-t p o    vhdl-template-port
C-c C-t p s    vhdl-template-process-seq
C-c C-t r p    vhdl-template-report
C-c C-t r t    vhdl-template-return
C-c C-t s i    vhdl-template-signal
C-c C-t s s    vhdl-template-selected-signal-asst
C-c C-t s u    vhdl-template-subtype
C-c C-t t y    vhdl-template-type
C-c C-t u s    vhdl-template-use
C-c C-t v a    vhdl-template-variable
C-c C-t w a    vhdl-template-wait
C-c C-t w c    vhdl-template-clocked-wait
C-c C-t w i    vhdl-template-with
C-c C-t w l    vhdl-template-while-loop
C-c C-u C-s    vhdl-update-sensitivity-list-process
C-c C-u M-s    vhdl-update-sensitivity-list-buffer
C-c C-v        vhdl-version(var)/vhdl-version(fun)
C-c C-x C-c    vhdl-fix-case-buffer
C-c C-x C-p    vhdl-fix-clause
C-c C-x C-s    vhdl-fix-statement-region
C-c C-x C-w    vhdl-fixup-whitespace-buffer
C-c C-x M-c    vhdl-fix-case-region
C-c C-x M-s    vhdl-fix-statement-buffer
C-c C-x M-w    vhdl-fixup-whitespace-region
C-c M--        vhdl-comment-display-line
C-c M-b        vhdl-beautify-region
C-c M-k        vhdl-generate-makefile
C-c M-m        vhdl-show-messages
C-c RET C-e    vhdl-electric-mode(var)/vhdl-electric-mode(fun)
C-c RET C-f    vhdl-compose-configuration
C-c RET C-k    vhdl-compose-components-package
C-c RET C-n    vhdl-compose-new-component
C-c RET C-p    vhdl-compose-place-component
C-c RET C-s    vhdl-stutter-mode(var)/vhdl-stutter-mode(fun)
C-c RET C-w    vhdl-compose-wire-components
C-c RET e      vhdl-model-example-model
C-c TAB C-b    vhdl-indent-buffer
C-c TAB C-d    vhdl-template-insert-directive
C-c TAB C-f    vhdl-fontify-buffer
C-c TAB C-g    vhdl-indent-group
C-c TAB C-l    indent-according-to-mode
C-c TAB C-p    vhdl-template-insert-package
C-c TAB C-s    vhdl-statistics-buffer
C-c TAB C-t    vhdl-template-insert-construct
C-c TAB RET    vhdl-model-insert
M-^            vhdl-delete-indentation
M-a            vhdl-beginning-of-statement
M-e            vhdl-end-of-statement
RET            vhdl-electric-return
SPC            vhdl-electric-space
TAB            vhdl-electric-tab
[              vhdl-electric-open-bracket
]              vhdl-electric-close-bracket