Function: verilog-read-sub-decls-sig

verilog-read-sub-decls-sig is a byte-compiled function defined in verilog-mode.el.gz.

Signature

(verilog-read-sub-decls-sig SUBMODDECLS PAR-VALUES COMMENT PORT SIG VEC MULTIDIM MEM)

Documentation

For verilog-read-sub-decls-line, add a signal.

Source Code

;; Defined in /usr/src/emacs/lisp/progmodes/verilog-mode.el.gz
(defun verilog-read-sub-decls-sig (submoddecls par-values comment port sig vec multidim mem)
  "For `verilog-read-sub-decls-line', add a signal."
  ;; sig eq t to indicate .name syntax
  ;;(message "vrsds: %s(%S)" port sig)
  (let ((dotname (eq sig t))
        portdata)
    (when sig
      (setq port (verilog-symbol-detick-denumber port))
      (setq sig  (if dotname port (verilog-symbol-detick-denumber sig)))
      (if vec (setq vec  (verilog-symbol-detick-denumber vec)))
      (if multidim (setq multidim  (mapcar #'verilog-symbol-detick-denumber multidim)))
      (if mem (setq mem (verilog-symbol-detick-denumber mem)))
      (unless (or (not sig)
                  (equal sig ""))  ; Ignore .foo(1'b1) assignments
	(cond ((or (setq portdata (assoc port (verilog-decls-get-inouts submoddecls)))
		   (equal "inout" verilog-read-sub-decls-gate-ios))
	       (setq sigs-inout
		     (cons (verilog-sig-new
			    sig
			    (if dotname (verilog-sig-bits portdata) vec)
			    (concat "To/From " comment)
                            mem
			    nil
			    (verilog-sig-signed portdata)
                            (verilog-read-sub-decls-type par-values portdata)
			    multidim nil)
			   sigs-inout)))
	      ((or (setq portdata (assoc port (verilog-decls-get-outputs submoddecls)))
		   (equal "output" verilog-read-sub-decls-gate-ios))
	       (setq sigs-out
		     (cons (verilog-sig-new
			    sig
			    (if dotname (verilog-sig-bits portdata) vec)
			    (concat "From " comment)
			    mem
			    nil
			    (verilog-sig-signed portdata)
			    ;; Though ok in SV, in V2K code, propagating the
			    ;;  "reg" in "output reg" upwards isn't legal.
			    ;; Also for backwards compatibility we don't propagate
			    ;;  "input wire" upwards.
			    ;; See also `verilog-signals-edit-wire-reg'.
                            (verilog-read-sub-decls-type par-values portdata)
			    multidim nil)
			   sigs-out)))
	      ((or (setq portdata (assoc port (verilog-decls-get-inputs submoddecls)))
		   (equal "input" verilog-read-sub-decls-gate-ios))
	       (setq sigs-in
		     (cons (verilog-sig-new
			    sig
			    (if dotname (verilog-sig-bits portdata) vec)
			    (concat "To " comment)
			    mem
			    nil
			    (verilog-sig-signed portdata)
                            (verilog-read-sub-decls-type par-values portdata)
			    multidim nil)
			   sigs-in)))
	      ((setq portdata (assoc port (verilog-decls-get-interfaces submoddecls)))
	       (setq sigs-intf
		     (cons (verilog-sig-new
			    sig
			    (if dotname (verilog-sig-bits portdata) vec)
			    (concat "To/From " comment)
			    mem
			    nil
			    (verilog-sig-signed portdata)
                            (verilog-read-sub-decls-type par-values portdata)
			    multidim nil)
			   sigs-intf)))
	      ((setq portdata (and verilog-read-sub-decls-in-interfaced
				   (assoc port (verilog-decls-get-vars submoddecls))))
	       (setq sigs-intfd
		     (cons (verilog-sig-new
			    sig
			    (if dotname (verilog-sig-bits portdata) vec)
			    (concat "To/From " comment)
			    mem
			    nil
			    (verilog-sig-signed portdata)
                            (verilog-read-sub-decls-type par-values portdata)
			    multidim nil)
			   sigs-intf)))
	      ;; (t  -- warning pin isn't defined.)   ; Leave for lint tool
	      )))))