Function: verilog-read-sub-decls

verilog-read-sub-decls is a byte-compiled function defined in verilog-mode.el.gz.

Signature

(verilog-read-sub-decls)

Documentation

Internally parse signals going to modules under this module.

Return an array of [ outputs inouts inputs ] signals for modules that are instantiated in this module. For example if declare A A (.B(SIG)) and SIG is an output, then SIG will be included in the list.

This only works on instantiations created with /*AUTOINST*/ converted by M-x verilog-auto-inst (verilog-auto-inst). Otherwise, it would have to read in the whole component library to determine connectivity of the design.

One work around for this problem is to manually create // Inputs and // Outputs comments above subcell signals, then have an empty AUTOINST, for example:

        submod SubModuleName (
            // Outputs
            .out (out),
            // Inputs
            .in (in)
            /*AUTOINST*/);

Source Code

;; Defined in /usr/src/emacs/lisp/progmodes/verilog-mode.el.gz
(defun verilog-read-sub-decls ()
  "Internally parse signals going to modules under this module.
Return an array of [ outputs inouts inputs ] signals for modules that are
instantiated in this module.  For example if declare A A (.B(SIG)) and SIG
is an output, then SIG will be included in the list.

This only works on instantiations created with /*AUTOINST*/ converted by
\\[verilog-auto-inst].  Otherwise, it would have to read in the whole
component library to determine connectivity of the design.

One work around for this problem is to manually create // Inputs
and // Outputs comments above subcell signals, then have an empty
AUTOINST, for example:

        submod SubModuleName (
            // Outputs
            .out (out),
            // Inputs
            .in  (in)
            /*AUTOINST*/);"
  (save-excursion
    (let ((end-mod-point (verilog-get-end-of-defun))
          st-point end-inst-point par-values
	  ;; below 3 modified by verilog-read-sub-decls-line
	  sigs-out sigs-inout sigs-in sigs-intf sigs-intfd)
      (verilog-beg-of-defun-quick)
      (while (verilog-re-search-forward-quick "\\(/\\*AUTOINST\\((.*?)\\)?\\*/\\|\\.\\*\\)" end-mod-point t)
	(save-excursion
	  (goto-char (match-beginning 0))
          (setq par-values (and verilog-auto-inst-param-value
                                verilog-auto-inst-param-value-type
                                (verilog-read-inst-param-value)))
	  (unless (verilog-inside-comment-or-string-p)
	    ;; Attempt to snarf a comment
	    (let* ((submod (verilog-read-inst-module))
		   (inst (verilog-read-inst-name))
		   (subprim (member submod verilog-gate-keywords))
		   (comment (concat inst " of " submod ".v"))
		   submodi submoddecls)
	      (cond
	       (subprim
		(setq submodi 'primitive
		      submoddecls (verilog-decls-new nil nil nil nil nil nil nil nil nil)
		      comment (concat inst " of " submod))
		(verilog-backward-open-paren)
		(setq end-inst-point (save-excursion (verilog-forward-sexp-ign-cmt 1)
						     (point))
		      st-point (point))
		(forward-char 1)
                (verilog-read-sub-decls-gate submoddecls par-values comment submod end-inst-point))
	       ;; Non-primitive
	       (t
		(when (setq submodi (verilog-modi-lookup submod t))
		  (setq submoddecls (verilog-modi-get-decls submodi)
			verilog-read-sub-decls-gate-ios nil)
		  (verilog-backward-open-paren)
		  (setq end-inst-point (save-excursion (verilog-forward-sexp-ign-cmt 1)
						       (point))
			st-point (point))
		  ;; This could have used a list created by verilog-auto-inst
		  ;; However I want it to be runnable even on user's manually added signals
		  (let ((verilog-read-sub-decls-in-interfaced t))
		    (while (re-search-forward "\\s *(?\\s *// Interfaced" end-inst-point t)
                      (verilog-read-sub-decls-line submoddecls par-values comment)))  ; Modifies sigs-ifd
		  (goto-char st-point)
		  (while (re-search-forward "\\s *(?\\s *// Interfaces" end-inst-point t)
                    (verilog-read-sub-decls-line submoddecls par-values comment))  ; Modifies sigs-out
		  (goto-char st-point)
		  (while (re-search-forward "\\s *(?\\s *// Outputs" end-inst-point t)
                    (verilog-read-sub-decls-line submoddecls par-values comment))  ; Modifies sigs-out
		  (goto-char st-point)
		  (while (re-search-forward "\\s *(?\\s *// Inouts" end-inst-point t)
                    (verilog-read-sub-decls-line submoddecls par-values comment))  ; Modifies sigs-inout
		  (goto-char st-point)
		  (while (re-search-forward "\\s *(?\\s *// Inputs" end-inst-point t)
                    (verilog-read-sub-decls-line submoddecls par-values comment))  ; Modifies sigs-in
		  )))))))
      ;; Combine duplicate bits
      ;;(setq rr (vector sigs-out sigs-inout sigs-in))
      (verilog-subdecls-new
       (verilog-signals-combine-bus (nreverse sigs-out))
       (verilog-signals-combine-bus (nreverse sigs-inout))
       (verilog-signals-combine-bus (nreverse sigs-in))
       (verilog-signals-combine-bus (nreverse sigs-intf))
       (verilog-signals-combine-bus (nreverse sigs-intfd))))))