Function: verilog-sk-define-signal

verilog-sk-define-signal is an interactive and byte-compiled function defined in verilog-mode.el.gz.

Signature

(verilog-sk-define-signal)

Documentation

Insert a definition of signal under point at top of module.

Key Bindings

Source Code

;; Defined in /usr/src/emacs/lisp/progmodes/verilog-mode.el.gz
(defun verilog-sk-define-signal ()
  "Insert a definition of signal under point at top of module."
  (interactive "*")
  (let* ((sig-chars "a-zA-Z0-9_")
	 (v1 (buffer-substring
              (save-excursion
                (skip-chars-backward sig-chars)
                (point))
              (save-excursion
                (skip-chars-forward sig-chars)
                (point)))))
    (if (not (member v1 verilog-keywords))
	(save-excursion
	  (setq verilog-sk-signal v1)
	  (verilog-beg-of-defun)
	  (verilog-end-of-statement)
	  (verilog-forward-syntactic-ws)
	  (verilog-sk-def-reg)
	  (message "signal at point is %s" v1))
      (message "object at point (%s) is a keyword" v1))))