Variable: vhdl-clock-edge-condition

vhdl-clock-edge-condition is a customizable variable defined in vhdl-mode.el.gz.

Value

standard

Documentation

Syntax of the clock edge condition.

  Standard: "clk\\='event and clk = \\='1\\='"
  Function: "rising_edge(clk)"

Source Code

;; Defined in /usr/src/emacs/lisp/progmodes/vhdl-mode.el.gz
(defcustom vhdl-clock-edge-condition 'standard
  "Syntax of the clock edge condition.
  Standard: \"clk\\='event and clk = \\='1\\='\"
  Function: \"rising_edge(clk)\""
  :type '(choice (const :tag "Standard" standard)
		 (const :tag "Function" function))
  :group 'vhdl-sequential-process)