Variable: vhdl-compiler-alist
vhdl-compiler-alist is a customizable variable defined in
vhdl-mode.el.gz.
Value
Large value
(("ADVance MS" "vacom" "-work \\1" "make" "-f \\1" nil "valib \\1; vamap \\2 \\1" "./" "work/" "Makefile" "adms"
("^\\s-+\\([0-9]+\\):\\s-+" nil 1 nil nil)
("^Compiling file \\(.+\\)" 1)
("ENTI/\\1.vif" "ARCH/\\1-\\2.vif" "CONF/\\1.vif" "PACK/\\1.vif" "BODY/\\1.vif" upcase))
("Aldec" "vcom" "-work \\1" "make" "-f \\1" nil "vlib \\1; vmap \\2 \\1" "./" "work/" "Makefile" "aldec"
("^.* ERROR [^:]+: \".*\" \"\\([^ \n]+\\)\" \\([0-9]+\\) \\([0-9]+\\)" 1 2 3 nil)
("" 0)
nil)
("Cadence Leapfrog" "cv" "-work \\1 -file" "make" "-f \\1" nil "mkdir \\1" "./" "work/" "Makefile" "leapfrog"
("^duluth: \\*E,[0-9]+ (\\([^ \n]+\\),\\([0-9]+\\)):" 1 2 nil nil)
("" 0)
("\\1/entity" "\\2/\\1" "\\1/configuration" "\\1/package" "\\1/body" downcase))
("Cadence NC" "ncvhdl" "-work \\1" "make" "-f \\1" nil "mkdir \\1" "./" "work/" "Makefile" "ncvhdl"
("^ncvhdl_p: \\*E,\\w+ (\\([^ \n]+\\),\\([0-9]+\\)|\\([0-9]+\\)):" 1 2 3 nil)
("" 0)
("\\1/entity/pc.db" "\\2/\\1/pc.db" "\\1/configuration/pc.db" "\\1/package/pc.db" "\\1/body/pc.db" downcase))
("GHDL" "ghdl" "-i --workdir=\\1 --ieee=synopsys -fexplicit " "make" "-f \\1" nil "mkdir \\1" "./" "work/" "Makefile" "ghdl"
("^ghdl_p: \\*E,\\w+ (\\([^ \n]+\\),\\([0-9]+\\)|\\([0-9]+\\)):" 1 2 3 nil)
("" 0)
("\\1/entity" "\\2/\\1" "\\1/configuration" "\\1/package" "\\1/body" downcase))
("IBM Compiler" "g2tvc" "-src" "precomp" "\\1" nil "mkdir \\1" "./" "work/" "Makefile" "ibm"
("^[0-9]+ COACHDL.*: File: \\([^ \n]+\\), *line.column: \\([0-9]+\\).\\([0-9]+\\)" 1 2 3 nil)
(" " 0)
nil)
("Ikos" "analyze" "-l \\1" "make" "-f \\1" nil "mkdir \\1" "./" "work/" "Makefile" "ikos"
("^E L\\([0-9]+\\)/C\\([0-9]+\\):" nil 1 2 nil)
("^analyze +\\(.+ +\\)*\\(.+\\)$" 2)
nil)
("ModelSim" "vcom" "-93 -work \\1" "make" "-f \\1" nil "vlib \\1; vmap \\2 \\1" "./" "work/" "Makefile" "modelsim"
("^\\(?:\\(?1:ERROR\\|\\*\\* Error\\)\\|\\(?2:WARNING\\|\\*\\* Warning\\)\\|\\(?3:NOTE\\|\\*\\* Note\\)\\)[^:]*:\\( *\\[[0-9]+]\\| ([^)]+)\\)? \\(?4:[^ \n]+\\)(\\(?5:[0-9]+\\)):" 4 5 nil
(2 . 3))
("" 0)
("\\1/_primary.dat" "\\2/\\1.dat" "\\1/_primary.dat" "\\1/_primary.dat" "\\1/body.dat" downcase))
("LEDA ProVHDL" "provhdl" "-w \\1 -f" "make" "-f \\1" nil "mkdir \\1" "./" "work/" "Makefile" "provhdl"
("^\\([^ \n:]+\\):\\([0-9]+\\): " 1 2 nil nil)
("" 0)
("ENTI/\\1.vif" "ARCH/\\1-\\2.vif" "CONF/\\1.vif" "PACK/\\1.vif" "BODY/BODY-\\1.vif" upcase))
("Quartus" "make" "-work \\1" "make" "-f \\1" nil "mkdir \\1" "./" "work/" "Makefile" "quartus"
("^\\(Error\\|Warning\\): .* \\([^ \n]+\\)(\\([0-9]+\\))" 2 3 nil nil)
("" 0)
nil)
("QuickHDL" "qvhcom" "-work \\1" "make" "-f \\1" nil "mkdir \\1" "./" "work/" "Makefile" "quickhdl"
("^\\(ERROR\\|WARNING\\)[^:]*: \\([^ \n]+\\)(\\([0-9]+\\)):" 2 3 nil nil)
("" 0)
("\\1/_primary.dat" "\\2/\\1.dat" "\\1/_primary.dat" "\\1/_primary.dat" "\\1/body.dat" downcase))
("Savant" "scram" "-publish-cc -design-library-name \\1" "make" "-f \\1" nil "mkdir \\1" "./" "work._savant_lib/" "Makefile" "savant"
("^\\([^ \n:]+\\):\\([0-9]+\\): " 1 2 nil nil)
("" 0)
("\\1_entity.vhdl" "\\2_secondary_units._savant_lib/\\2_\\1.vhdl" "\\1_config.vhdl" "\\1_package.vhdl" "\\1_secondary_units._savant_lib/\\1_package_body.vhdl" downcase))
("Simili" "vhdlp" "-work \\1" "make" "-f \\1" nil "mkdir \\1" "./" "work/" "Makefile" "simili"
("^\\(Error\\|Warning\\): \\w+: \\([^ \n]+\\): (line \\([0-9]+\\)): " 2 3 nil nil)
("" 0)
("\\1/prim.var" "\\2/_\\1.var" "\\1/prim.var" "\\1/prim.var" "\\1/_body.var" downcase))
("Speedwave" "analyze" "-libfile vsslib.ini -src" "make" "-f \\1" nil "mkdir \\1" "./" "work/" "Makefile" "speedwave"
("^ *ERROR\\[[0-9]+]::File \\([^ \n]+\\) Line \\([0-9]+\\):" 1 2 nil nil)
("" 0)
nil)
("Synopsys" "vhdlan" "-nc -work \\1" "make" "-f \\1" nil "mkdir \\1" "./" "work/" "Makefile" "synopsys"
("^\\*\\*Error: vhdlan,[0-9]+ \\([^ \n]+\\)(\\([0-9]+\\)):" 1 2 nil nil)
("" 0)
("\\1.sim" "\\2__\\1.sim" "\\1.sim" "\\1.sim" "\\1__.sim" upcase))
("Synopsys Design Compiler" "vhdlan" "-nc -spc -work \\1" "make" "-f \\1" nil "mkdir \\1" "./" "work/" "Makefile" "synopsys_dc"
("^\\*\\*Error: vhdlan,[0-9]+ \\([^ \n]+\\)(\\([0-9]+\\)):" 1 2 nil nil)
("" 0)
("\\1.syn" "\\2__\\1.syn" "\\1.syn" "\\1.syn" "\\1__.syn" upcase))
("Synplify" "n/a" "n/a" "make" "-f \\1" nil "mkdir \\1" "./" "work/" "Makefile" "synplify"
("^@[EWN]:\"\\([^ \n]+\\)\":\\([0-9]+\\):\\([0-9]+\\):" 1 2 3 nil)
("" 0)
nil)
("Vantage" "analyze" "-libfile vsslib.ini -src" "make" "-f \\1" nil "mkdir \\1" "./" "work/" "Makefile" "vantage"
("^\\*\\*Error: LINE \\([0-9]+\\) \\*\\*\\*" nil 1 nil nil)
("^ *Compiling \"\\(.+\\)\" " 1)
nil)
("VeriBest" "vc" "vhdl" "make" "-f \\1" nil "mkdir \\1" "./" "work/" "Makefile" "veribest"
("^ +\\([0-9]+\\): +[^ ]" nil 1 nil nil)
("" 0)
nil)
("Viewlogic" "analyze" "-libfile vsslib.ini -src" "make" "-f \\1" nil "mkdir \\1" "./" "work/" "Makefile" "viewlogic"
("^\\*\\*Error: LINE \\([0-9]+\\) \\*\\*\\*" nil 1 nil nil)
("^ *Compiling \"\\(.+\\)\" " 1)
nil)
("Xilinx XST" "xflow" "" "make" "-f \\1" nil "mkdir \\1" "./" "work/" "Makefile" "xilinx"
("^ERROR:HDLParsers:[0-9]+ - \"\\([^ \n]+\\)\" Line \\([0-9]+\\)\\." 1 2 nil nil)
("" 0)
nil)
("Xilinx Vivado" "xvhdl" "" "make" "-f \\1" nil "mkdir \\1" "./" "work/" "Makefile" "vivado"
("^\\(?:\\(?1:ERROR\\)\\|\\(?2:WARNING\\)\\|\\(?3:INFO\\)\\): \\(.+\\) \\[\\(?4:[^ \n]+\\):\\(?5:[0-9]+\\)\\]" 4 5 nil
(2 . 3))
("" 0)
("\\1/entity" "\\2/\\1" "\\1/configuration" "\\1/package" "\\1/body" downcase)))
Documentation
List of available VHDL compilers and their properties.
Each list entry specifies the following items for a compiler:
Compiler:
Compiler name : name used in option vhdl-compiler to choose compiler
Compile command : command used for source file compilation
Compile options : compile options ("\\1" inserts library name)
Make command : command used for compilation using a Makefile
Make options : make options ("\\1" inserts Makefile name)
Generate Makefile: use built-in function or command to generate a Makefile
("\\1" inserts Makefile name, "\\2" inserts library name)
Library command : command to create library directory ("\\1" inserts
library directory, "\\2" inserts library name)
Compile directory: where compilation is run and the Makefile is placed
Library directory: directory of default library
Makefile name : name of Makefile (default is "Makefile")
ID string : compiler identification string (see vhdl-project-alist)
Error message:
Regexp : regular expression to match error messages (*)
File subexp index: index of subexpression that matches the file name
Line subexp index: index of subexpression that matches the line number
Column subexp idx: index of subexpression that matches the column number
Type subexp : message type, can be nil for a real error, 1 for warning
or 0 for info. Type can also be detected using the form
(WARNING . INFO). In that case this will be equivalent to
1 if the WARNING’th subexpression matched or else
equivalent to 0 if the INFO’th subexpression matched, or
else equivalent to nil if neither of them matched. See
also compilation-error-regexp-alist.
File message:
Regexp : regular expression to match a file name message
File subexp index: index of subexpression that matches the file name
Unit-to-file name mapping: mapping of library unit names to names of files
generated by the compiler (used for Makefile generation)
To string : string a name is mapped to ("\\1" inserts the unit name,
"\\2" inserts the entity name for architectures,
"\\3" inserts the library name)
Case adjustment : adjust case of inserted unit names
(*) The regular expression must match the error message starting from the
beginning of the line (but not necessarily to the end of the line).
Compile options allows insertion of the library name (see vhdl-project-alist)
in order to set the compilers library option (e.g. "vcom -work my_lib").
For Makefile generation, the built-in function can be used (requires
specification of the unit-to-file name mapping). Alternatively, an
external command can be specified. Work directory allows specification of
an alternative "work" library path (e.g. "WORK/" instead of "work/",
used for Makefile generation). To use another library name than "work",
customize vhdl-project-alist. The library command is inserted in Makefiles
to automatically create the library directory if not existent.
Compile options, compile directory, library directory, and Makefile name are
overwritten by the project settings if a project is defined (see
vhdl-project-alist). Directory paths are relative to the source file
directory.
Some compilers do not include the file name in the error message, but print
out a file name message in advance. In this case, set "File Subexp Index"
under "Error Message" to 0 and fill out the "File Message" entries.
If no file name at all is printed out, set both "File Message" entries to 0
(a default file name message will be printed out instead, does not work in
XEmacs).
A compiler is selected for syntax analysis (M-x vhdl-compile (vhdl-compile)) by
assigning its name to option vhdl-compiler.
Please send any missing or erroneous compiler properties to the maintainer for updating.
NOTE: Activate new error and file message regexps and reflect the new setting
in the choice list of option vhdl-compiler by restarting Emacs.
This variable was added, or its default value changed, in Emacs 24.4.
Source Code
;; Defined in /usr/src/emacs/lisp/progmodes/vhdl-mode.el.gz
(defcustom vhdl-compiler-alist
'(
;; 60: docal <= false;
;; ^^^^^
;; [Error] Assignment error: variable is illegal target of signal assignment
("ADVance MS" "vacom" "-work \\1" "make" "-f \\1"
nil "valib \\1; vamap \\2 \\1" "./" "work/" "Makefile" "adms"
("^\\s-+\\([0-9]+\\):\\s-+" nil 1 nil nil) ("^Compiling file \\(.+\\)" 1)
("ENTI/\\1.vif" "ARCH/\\1-\\2.vif" "CONF/\\1.vif"
"PACK/\\1.vif" "BODY/\\1.vif" upcase))
;; Aldec
;; COMP96 ERROR COMP96_0018: "Identifier expected." "test.vhd" 66 3
("Aldec" "vcom" "-work \\1" "make" "-f \\1"
nil "vlib \\1; vmap \\2 \\1" "./" "work/" "Makefile" "aldec"
("^.* ERROR [^:]+: \".*\" \"\\([^ \t\n]+\\)\" \\([0-9]+\\) \\([0-9]+\\)" 1 2 3 nil) ("" 0)
nil)
;; Cadence Leapfrog: cv -file test.vhd
;; duluth: *E,430 (test.vhd,13): identifier (POSITIV) is not declared
("Cadence Leapfrog" "cv" "-work \\1 -file" "make" "-f \\1"
nil "mkdir \\1" "./" "work/" "Makefile" "leapfrog"
("^duluth: \\*E,[0-9]+ (\\([^ \t\n]+\\),\\([0-9]+\\)):" 1 2 nil nil) ("" 0)
("\\1/entity" "\\2/\\1" "\\1/configuration"
"\\1/package" "\\1/body" downcase))
;; Cadence Affirma NC vhdl: ncvhdl test.vhd
;; ncvhdl_p: *E,IDENTU (test.vhd,13|25): identifier
;; (PLL_400X_TOP) is not declared [10.3].
("Cadence NC" "ncvhdl" "-work \\1" "make" "-f \\1"
nil "mkdir \\1" "./" "work/" "Makefile" "ncvhdl"
("^ncvhdl_p: \\*E,\\w+ (\\([^ \t\n]+\\),\\([0-9]+\\)|\\([0-9]+\\)):" 1 2 3 nil) ("" 0)
("\\1/entity/pc.db" "\\2/\\1/pc.db" "\\1/configuration/pc.db"
"\\1/package/pc.db" "\\1/body/pc.db" downcase))
;; ghdl vhdl
;; ghdl -a bad_counter.vhdl
;; bad_counter.vhdl:13:14: operator "=" is overloaded
("GHDL" "ghdl" "-i --workdir=\\1 --ieee=synopsys -fexplicit " "make" "-f \\1"
nil "mkdir \\1" "./" "work/" "Makefile" "ghdl"
("^ghdl_p: \\*E,\\w+ (\\([^ \t\n]+\\),\\([0-9]+\\)|\\([0-9]+\\)):" 1 2 3 nil) ("" 0)
("\\1/entity" "\\2/\\1" "\\1/configuration"
"\\1/package" "\\1/body" downcase))
;; IBM Compiler
;; 00 COACHDL* | [CCHDL-1]: File: adder.vhd, line.column: 120.6
("IBM Compiler" "g2tvc" "-src" "precomp" "\\1"
nil "mkdir \\1" "./" "work/" "Makefile" "ibm"
("^[0-9]+ COACHDL.*: File: \\([^ \t\n]+\\), *line.column: \\([0-9]+\\).\\([0-9]+\\)" 1 2 3 nil) (" " 0)
nil)
;; Ikos Voyager: analyze test.vhd
;; analyze test.vhd
;; E L4/C5: this library unit is inaccessible
("Ikos" "analyze" "-l \\1" "make" "-f \\1"
nil "mkdir \\1" "./" "work/" "Makefile" "ikos"
("^E L\\([0-9]+\\)/C\\([0-9]+\\):" nil 1 2 nil)
("^analyze +\\(.+ +\\)*\\(.+\\)$" 2)
nil)
;; ModelSim, Model Technology: vcom test.vhd
;; ERROR: test.vhd(14): Unknown identifier: positiv
;; WARNING[2]: test.vhd(85): Possible infinite loop
;; ** Warning: [4] ../src/emacsvsim.vhd(43): An abstract ...
;; ** Error: adder.vhd(190): Unknown identifier: ctl_numb
;; ** Error: counter_rtl.vhd(18): Nonresolved signal 'hallo' has multiple sources.
;; Drivers:
;; counter_rtl.vhd(27):Conditional signal assignment line__27
;; counter_rtl.vhd(29):Conditional signal assignment line__29
("ModelSim" "vcom" "-93 -work \\1" "make" "-f \\1"
nil "vlib \\1; vmap \\2 \\1" "./" "work/" "Makefile" "modelsim"
("^\\(?:\\(?1:ERROR\\|\\*\\* Error\\)\\|\\(?2:WARNING\\|\\*\\* Warning\\)\\|\\(?3:NOTE\\|\\*\\* Note\\)\\)[^:]*:\\( *\\[[0-9]+]\\| ([^)]+)\\)? \\(?4:[^ \t\n]+\\)(\\(?5:[0-9]+\\)):" 4 5 nil (2 . 3))
("" 0)
("\\1/_primary.dat" "\\2/\\1.dat" "\\1/_primary.dat"
"\\1/_primary.dat" "\\1/body.dat" downcase))
;; ProVHDL, Synopsys LEDA: provhdl -w work -f test.vhd
;; test.vhd:34: error message
("LEDA ProVHDL" "provhdl" "-w \\1 -f" "make" "-f \\1"
nil "mkdir \\1" "./" "work/" "Makefile" "provhdl"
("^\\([^ \t\n:]+\\):\\([0-9]+\\): " 1 2 nil nil) ("" 0)
("ENTI/\\1.vif" "ARCH/\\1-\\2.vif" "CONF/\\1.vif"
"PACK/\\1.vif" "BODY/BODY-\\1.vif" upcase))
;; Quartus compiler
;; Error: VHDL error at dvi2sdi.vhd(473): object k2_alto_out_lvl is used
;; Error: Verilog HDL syntax error at otsuif_v1_top.vhd(147) near text
;; Error: VHDL syntax error at otsuif_v1_top.vhd(147): clk_ is an illegal
;; Error: VHDL Use Clause error at otsuif_v1_top.vhd(455): design library
;; Warning: VHDL Process Statement warning at dvi2sdi_tst.vhd(172): ...
("Quartus" "make" "-work \\1" "make" "-f \\1"
nil "mkdir \\1" "./" "work/" "Makefile" "quartus"
("^\\(Error\\|Warning\\): .* \\([^ \t\n]+\\)(\\([0-9]+\\))" 2 3 nil nil) ("" 0)
nil)
;; QuickHDL, Mentor Graphics: qvhcom test.vhd
;; ERROR: test.vhd(24): near "dnd": expecting: END
;; WARNING[4]: test.vhd(30): A space is required between ...
("QuickHDL" "qvhcom" "-work \\1" "make" "-f \\1"
nil "mkdir \\1" "./" "work/" "Makefile" "quickhdl"
("^\\(ERROR\\|WARNING\\)[^:]*: \\([^ \t\n]+\\)(\\([0-9]+\\)):" 2 3 nil nil) ("" 0)
("\\1/_primary.dat" "\\2/\\1.dat" "\\1/_primary.dat"
"\\1/_primary.dat" "\\1/body.dat" downcase))
;; Savant: scram -publish-cc test.vhd
;; test.vhd:87: _set_passed_through_out_port(IIR_Boolean) not defined for
("Savant" "scram" "-publish-cc -design-library-name \\1" "make" "-f \\1"
nil "mkdir \\1" "./" "work._savant_lib/" "Makefile" "savant"
("^\\([^ \t\n:]+\\):\\([0-9]+\\): " 1 2 nil nil) ("" 0)
("\\1_entity.vhdl" "\\2_secondary_units._savant_lib/\\2_\\1.vhdl"
"\\1_config.vhdl" "\\1_package.vhdl"
"\\1_secondary_units._savant_lib/\\1_package_body.vhdl" downcase))
;; Simili: vhdlp -work test.vhd
;; Error: CSVHDL0002: test.vhd: (line 97): Invalid prefix
("Simili" "vhdlp" "-work \\1" "make" "-f \\1"
nil "mkdir \\1" "./" "work/" "Makefile" "simili"
("^\\(Error\\|Warning\\): \\w+: \\([^ \t\n]+\\): (line \\([0-9]+\\)): " 2 3 nil nil) ("" 0)
("\\1/prim.var" "\\2/_\\1.var" "\\1/prim.var"
"\\1/prim.var" "\\1/_body.var" downcase))
;; Speedwave (Innoveda): analyze -libfile vsslib.ini -src test.vhd
;; ERROR[11]::File test.vhd Line 100: Use of undeclared identifier
("Speedwave" "analyze" "-libfile vsslib.ini -src" "make" "-f \\1"
nil "mkdir \\1" "./" "work/" "Makefile" "speedwave"
("^ *ERROR\\[[0-9]+]::File \\([^ \t\n]+\\) Line \\([0-9]+\\):" 1 2 nil nil) ("" 0)
nil)
;; Synopsys, VHDL Analyzer (sim): vhdlan -nc test.vhd
;; **Error: vhdlan,703 test.vhd(22): OTHERS is not legal in this context.
("Synopsys" "vhdlan" "-nc -work \\1" "make" "-f \\1"
nil "mkdir \\1" "./" "work/" "Makefile" "synopsys"
("^\\*\\*Error: vhdlan,[0-9]+ \\([^ \t\n]+\\)(\\([0-9]+\\)):" 1 2 nil nil) ("" 0)
("\\1.sim" "\\2__\\1.sim" "\\1.sim" "\\1.sim" "\\1__.sim" upcase))
;; Synopsys, VHDL Analyzer (syn): vhdlan -nc -spc test.vhd
;; **Error: vhdlan,703 test.vhd(22): OTHERS is not legal in this context.
("Synopsys Design Compiler" "vhdlan" "-nc -spc -work \\1" "make" "-f \\1"
nil "mkdir \\1" "./" "work/" "Makefile" "synopsys_dc"
("^\\*\\*Error: vhdlan,[0-9]+ \\([^ \t\n]+\\)(\\([0-9]+\\)):" 1 2 nil nil) ("" 0)
("\\1.syn" "\\2__\\1.syn" "\\1.syn" "\\1.syn" "\\1__.syn" upcase))
;; Synplify:
;; @W:"test.vhd":57:8:57:9|Optimizing register bit count_x(5) to a constant 0
("Synplify" "n/a" "n/a" "make" "-f \\1"
nil "mkdir \\1" "./" "work/" "Makefile" "synplify"
("^@[EWN]:\"\\([^ \t\n]+\\)\":\\([0-9]+\\):\\([0-9]+\\):" 1 2 3 nil) ("" 0)
nil)
;; Vantage: analyze -libfile vsslib.ini -src test.vhd
;; Compiling "test.vhd" line 1...
;; **Error: LINE 49 *** No aggregate value is valid in this context.
("Vantage" "analyze" "-libfile vsslib.ini -src" "make" "-f \\1"
nil "mkdir \\1" "./" "work/" "Makefile" "vantage"
("^\\*\\*Error: LINE \\([0-9]+\\) \\*\\*\\*" nil 1 nil nil)
("^ *Compiling \"\\(.+\\)\" " 1)
nil)
;; VeriBest: vc vhdl test.vhd
;; (no file name printed out!)
;; 32: Z <= A and BitA ;
;; ^^^^
;; [Error] Name BITA is unknown
("VeriBest" "vc" "vhdl" "make" "-f \\1"
nil "mkdir \\1" "./" "work/" "Makefile" "veribest"
("^ +\\([0-9]+\\): +[^ ]" nil 1 nil nil) ("" 0)
nil)
;; Viewlogic: analyze -libfile vsslib.ini -src test.vhd
;; Compiling "test.vhd" line 1...
;; **Error: LINE 49 *** No aggregate value is valid in this context.
("Viewlogic" "analyze" "-libfile vsslib.ini -src" "make" "-f \\1"
nil "mkdir \\1" "./" "work/" "Makefile" "viewlogic"
("^\\*\\*Error: LINE \\([0-9]+\\) \\*\\*\\*" nil 1 nil nil)
("^ *Compiling \"\\(.+\\)\" " 1)
nil)
;; Xilinx XST:
;; ERROR:HDLParsers:164 - "test.vhd" Line 3. parse error
("Xilinx XST" "xflow" "" "make" "-f \\1"
nil "mkdir \\1" "./" "work/" "Makefile" "xilinx"
("^ERROR:HDLParsers:[0-9]+ - \"\\([^ \t\n]+\\)\" Line \\([0-9]+\\)\\." 1 2 nil nil) ("" 0)
nil)
;; Xilinx Vivado:
;; ERROR: [VRFC 10-1412] syntax error near o_idle [test.vhd:23]
("Xilinx Vivado" "xvhdl" "" "make" "-f \\1"
nil "mkdir \\1" "./" "work/" "Makefile" "vivado"
("^\\(?:\\(?1:ERROR\\)\\|\\(?2:WARNING\\)\\|\\(?3:INFO\\)\\): \\(.+\\) \\[\\(?4:[^ \t\n]+\\):\\(?5:[0-9]+\\)\\]" 4 5 nil (2 . 3)) ("" 0)
("\\1/entity" "\\2/\\1" "\\1/configuration"
"\\1/package" "\\1/body" downcase))
)
"List of available VHDL compilers and their properties.
Each list entry specifies the following items for a compiler:
Compiler:
Compiler name : name used in option `vhdl-compiler' to choose compiler
Compile command : command used for source file compilation
Compile options : compile options (\"\\1\" inserts library name)
Make command : command used for compilation using a Makefile
Make options : make options (\"\\1\" inserts Makefile name)
Generate Makefile: use built-in function or command to generate a Makefile
(\"\\1\" inserts Makefile name, \"\\2\" inserts library name)
Library command : command to create library directory (\"\\1\" inserts
library directory, \"\\2\" inserts library name)
Compile directory: where compilation is run and the Makefile is placed
Library directory: directory of default library
Makefile name : name of Makefile (default is \"Makefile\")
ID string : compiler identification string (see `vhdl-project-alist')
Error message:
Regexp : regular expression to match error messages (*)
File subexp index: index of subexpression that matches the file name
Line subexp index: index of subexpression that matches the line number
Column subexp idx: index of subexpression that matches the column number
Type subexp : message type, can be nil for a real error, 1 for warning
or 0 for info. Type can also be detected using the form
(WARNING . INFO). In that case this will be equivalent to
1 if the WARNING’th subexpression matched or else
equivalent to 0 if the INFO’th subexpression matched, or
else equivalent to nil if neither of them matched. See
also `compilation-error-regexp-alist'.
File message:
Regexp : regular expression to match a file name message
File subexp index: index of subexpression that matches the file name
Unit-to-file name mapping: mapping of library unit names to names of files
generated by the compiler (used for Makefile generation)
To string : string a name is mapped to (\"\\1\" inserts the unit name,
\"\\2\" inserts the entity name for architectures,
\"\\3\" inserts the library name)
Case adjustment : adjust case of inserted unit names
\(*) The regular expression must match the error message starting from the
beginning of the line (but not necessarily to the end of the line).
Compile options allows insertion of the library name (see `vhdl-project-alist')
in order to set the compilers library option (e.g. \"vcom -work my_lib\").
For Makefile generation, the built-in function can be used (requires
specification of the unit-to-file name mapping). Alternatively, an
external command can be specified. Work directory allows specification of
an alternative \"work\" library path (e.g. \"WORK/\" instead of \"work/\",
used for Makefile generation). To use another library name than \"work\",
customize `vhdl-project-alist'. The library command is inserted in Makefiles
to automatically create the library directory if not existent.
Compile options, compile directory, library directory, and Makefile name are
overwritten by the project settings if a project is defined (see
`vhdl-project-alist'). Directory paths are relative to the source file
directory.
Some compilers do not include the file name in the error message, but print
out a file name message in advance. In this case, set \"File Subexp Index\"
under \"Error Message\" to 0 and fill out the \"File Message\" entries.
If no file name at all is printed out, set both \"File Message\" entries to 0
\(a default file name message will be printed out instead, does not work in
XEmacs).
A compiler is selected for syntax analysis (`\\[vhdl-compile]') by
assigning its name to option `vhdl-compiler'.
Please send any missing or erroneous compiler properties to the maintainer for
updating.
NOTE: Activate new error and file message regexps and reflect the new setting
in the choice list of option `vhdl-compiler' by restarting Emacs."
:type '(repeat
(list :tag "Compiler" :indent 2
(string :tag "Compiler name ")
(string :tag "Compile command ")
(string :tag "Compile options " "-work \\1")
(string :tag "Make command " "make")
(string :tag "Make options " "-f \\1")
(choice :tag "Generate Makefile "
(const :tag "Built-in function" nil)
(string :tag "Command" "vmake \\2 > \\1"))
(string :tag "Library command " "mkdir \\1")
(directory :tag "Compile directory "
:validate vhdl-widget-directory-validate "./")
(directory :tag "Library directory "
:validate vhdl-widget-directory-validate "work/")
(file :tag "Makefile name " "Makefile")
(string :tag "ID string ")
(list :tag "Error message" :indent 4
(regexp :tag "Regexp ")
(choice :tag "File subexp "
(integer :tag "Index")
(const :tag "No file name" nil))
(integer :tag "Line subexp index")
(choice :tag "Column subexp "
(integer :tag "Index")
(const :tag "No column number" nil))
(choice :tag "Type "
(const :tag "Info" 0)
(const :tag "Warning" 1)
(const :tag "Error" nil)
(cons :tag "Type detection"
(natnum :tag "Warning subexp index")
(natnum :tag "Info subexp index "))))
(list :tag "File message" :indent 4
(regexp :tag "Regexp ")
(integer :tag "File subexp index"))
(choice :tag "Unit-to-file name mapping"
:format "%t: %[Value Menu%] %v\n"
(const :tag "Not defined" nil)
(list :tag "To string" :indent 4
(string :tag "Entity " "\\1.vhd")
(string :tag "Architecture " "\\2_\\1.vhd")
(string :tag "Configuration " "\\1.vhd")
(string :tag "Package " "\\1.vhd")
(string :tag "Package Body " "\\1_body.vhd")
(choice :tag "Case adjustment "
(const :tag "None" identity)
(const :tag "Upcase" upcase)
(const :tag "Downcase" downcase))))))
:set (lambda (variable value)
(vhdl-custom-set variable value #'vhdl-update-mode-menu))
:version "24.4"
:group 'vhdl-compile)