Variable: vhdl-testbench-declarations

vhdl-testbench-declarations is a customizable variable defined in vhdl-mode.el.gz.

Value

"  -- clock\n  signal Clk : std_logic := '1';\n"

Documentation

String or file to be inserted in the testbench declarative part.

If the string specifies an existing file name, the contents of the file is inserted, otherwise the string itself is inserted in the testbench architecture before the BEGIN keyword. Type C-j for newlines.

Source Code

;; Defined in /usr/src/emacs/lisp/progmodes/vhdl-mode.el.gz
(defcustom vhdl-testbench-declarations "\
  -- clock
  signal Clk : std_logic := '1';
"
  "String or file to be inserted in the testbench declarative part.
If the string specifies an existing file name, the contents of the file is
inserted, otherwise the string itself is inserted in the testbench
architecture before the BEGIN keyword.
Type `C-j' for newlines."
  :type 'string
  :group 'vhdl-testbench)