Function: verilog-auto-inout-comp

verilog-auto-inout-comp is a byte-compiled function defined in verilog-mode.el.gz.

Signature

(verilog-auto-inout-comp)

Documentation

Expand AUTOINOUTCOMP statements, as part of M-x verilog-auto (verilog-auto).

Take input/output/inout statements from the specified module and insert the inverse into the current module (inputs become outputs
and vice-versa.) This is useful for making test and stimulus
modules which need to have complementing I/O with another module. Any I/O which are already defined in this module will not be redefined. For the complement of this function, see verilog-auto-inout-module.

Limitations:
  If placed inside the parenthesis of a module declaration, it creates
  Verilog 2001 style, else uses Verilog 1995 style.

  Concatenation and outputting partial buses is not supported.

  Module names must be resolvable to filenames. See verilog-auto-inst.

  Signals are not inserted in the same order as in the original module,
  though they will appear to be in the same order to an AUTOINST
  instantiating either module.

An example:

        module ExampMain
          (input i,
           output o,
           inout io);
        endmodule

        module ExampBench (/*AUTOARG*/);
           /*AUTOINOUTCOMP("ExampMain")*/
        endmodule

Typing M-x verilog-auto (verilog-auto) will make this into:

        module ExampShell (/*AUTOARG*/i, io, o);
           /*AUTOINOUTCOMP("ExampMain")*/
           // Beginning of automatic in/out/inouts
           output i;
           inout io;
           input o;
           // End of automatics
        endmodule

You may also provide an optional regular expression, in which case only signals matching the regular expression will be included. For example the same expansion will result from only extracting signals starting with i:

           /*AUTOINOUTCOMP("ExampMain","^i")*/

You may also provide an optional third argument regular expression, in which case only signals which have that pin direction and data type matching that regular expression will be included. This matches against everything before the signal name in the declaration, for example against "input" (single bit), "output logic" (direction and type) or "output [1:0]" (direction and implicit type). You also probably want to skip spaces in your regexp.

For example, the below will result in matching the output "o" against the previous example's module:

           /*AUTOINOUTCOMP("ExampMain","","^output.*")*/

You may also provide an optional fourth argument regular expression, which if not "" only signals which do NOT match that expression are included.

Source Code

;; Defined in /usr/src/emacs/lisp/progmodes/verilog-mode.el.gz
(defun verilog-auto-inout-comp ()
  "Expand AUTOINOUTCOMP statements, as part of \\[verilog-auto].
Take input/output/inout statements from the specified module and
insert the inverse into the current module (inputs become outputs
and vice-versa.)  This is useful for making test and stimulus
modules which need to have complementing I/O with another module.
Any I/O which are already defined in this module will not be
redefined.  For the complement of this function, see
`verilog-auto-inout-module'.

Limitations:
  If placed inside the parenthesis of a module declaration, it creates
  Verilog 2001 style, else uses Verilog 1995 style.

  Concatenation and outputting partial buses is not supported.

  Module names must be resolvable to filenames.  See `verilog-auto-inst'.

  Signals are not inserted in the same order as in the original module,
  though they will appear to be in the same order to an AUTOINST
  instantiating either module.

An example:

        module ExampMain
          (input i,
           output o,
           inout io);
        endmodule

        module ExampBench (/*AUTOARG*/);
           /*AUTOINOUTCOMP(\"ExampMain\")*/
        endmodule

Typing \\[verilog-auto] will make this into:

        module ExampShell (/*AUTOARG*/i, io, o);
           /*AUTOINOUTCOMP(\"ExampMain\")*/
           // Beginning of automatic in/out/inouts
           output i;
           inout io;
           input o;
           // End of automatics
        endmodule

You may also provide an optional regular expression, in which case only
signals matching the regular expression will be included.  For example the
same expansion will result from only extracting signals starting with i:

           /*AUTOINOUTCOMP(\"ExampMain\",\"^i\")*/

You may also provide an optional third argument regular
expression, in which case only signals which have that pin
direction and data type matching that regular expression will be
included.  This matches against everything before the signal name
in the declaration, for example against \"input\" (single
bit), \"output logic\" (direction and type)
or \"output [1:0]\" (direction and implicit type).  You also
probably want to skip spaces in your regexp.

For example, the below will result in matching the output \"o\"
against the previous example's module:

           /*AUTOINOUTCOMP(\"ExampMain\",\"\",\"^output.*\")*/

You may also provide an optional fourth argument regular
expression, which if not \"\" only signals which do NOT match
that expression are included."
  ;; Beware spacing of quotes in above as can mess up Emacs indenter
  (verilog-auto-inout-module t nil))