Function: verilog-auto-inout

verilog-auto-inout is a byte-compiled function defined in verilog-mode.el.gz.

Signature

(verilog-auto-inout)

Documentation

Expand AUTOINOUT statements, as part of M-x verilog-auto (verilog-auto).

Make inout statements for any inout signal in an /*AUTOINST*/ that isn't declared elsewhere inside the module.

Limitations:
  This ONLY detects inouts of AUTOINSTants (see verilog-read-sub-decls).

  If placed inside the parenthesis of a module declaration, it creates
  Verilog 2001 style, else uses Verilog 1995 style.

  If any concatenation, or bit-subscripts are missing in the AUTOINSTant's
  instantiation, all bets are off. (For example due to an AUTO_TEMPLATE).

  Typedefs must match verilog-typedef-regexp, which is disabled by default.

  Types are added to declarations if an AUTOLOGIC or
  verilog-auto-wire-type is set to logic.

  Signals matching verilog-auto-inout-ignore-regexp are not included.

An example (see verilog-auto-inst for what else is going on here):

        module InstModule (inout io);
        endmodule

        module ExampInout (
           /*AUTOINOUT*/
           );
           InstModule instName
             (/*AUTOINST*/);
        endmodule

Typing M-x verilog-auto (verilog-auto) will make this into:

        module ExampInout (
           /*AUTOINOUT*/
           // Beginning of automatic inouts
           inout io // To/From instName of InstModule.v
           // End of automatics
           );
           InstModule instName
             (/*AUTOINST*/
              // Inouts
              .io (io));
        endmodule

You may also provide an optional regular expression, in which case only signals matching the regular expression will be included, or excluded if the regexp begins with ?! (question-mark exclamation-mark). For example the same expansion will result from only extracting inouts starting with i:

           /*AUTOINOUT("^i")*/

Source Code

;; Defined in /usr/src/emacs/lisp/progmodes/verilog-mode.el.gz
(defun verilog-auto-inout ()
  "Expand AUTOINOUT statements, as part of \\[verilog-auto].
Make inout statements for any inout signal in an /*AUTOINST*/ that
isn't declared elsewhere inside the module.

Limitations:
  This ONLY detects inouts of AUTOINSTants (see `verilog-read-sub-decls').

  If placed inside the parenthesis of a module declaration, it creates
  Verilog 2001 style, else uses Verilog 1995 style.

  If any concatenation, or bit-subscripts are missing in the AUTOINSTant's
  instantiation, all bets are off.  (For example due to an AUTO_TEMPLATE).

  Typedefs must match `verilog-typedef-regexp', which is disabled by default.

  Types are added to declarations if an AUTOLOGIC or
  `verilog-auto-wire-type' is set to logic.

  Signals matching `verilog-auto-inout-ignore-regexp' are not included.

An example (see `verilog-auto-inst' for what else is going on here):

        module InstModule (inout io);
        endmodule

        module ExampInout (
           /*AUTOINOUT*/
           );
           InstModule instName
             (/*AUTOINST*/);
        endmodule

Typing \\[verilog-auto] will make this into:

        module ExampInout (
           /*AUTOINOUT*/
           // Beginning of automatic inouts
           inout           io      // To/From instName of InstModule.v
           // End of automatics
           );
           InstModule instName
             (/*AUTOINST*/
              // Inouts
              .io       (io));
        endmodule

You may also provide an optional regular expression, in which
case only signals matching the regular expression will be
included, or excluded if the regexp begins with ?! (question-mark
exclamation-mark).  For example the same expansion will result
from only extracting inouts starting with i:

           /*AUTOINOUT(\"^i\")*/"
  (save-excursion
    ;; Point must be at insertion point.
    (let* ((indent-pt (current-indentation))
	   (params (verilog-read-auto-params 0 1))
	   (regexp (nth 0 params))
	   (v2k  (verilog-in-paren-quick))
	   (modi (verilog-modi-current))
	   (moddecls (verilog-modi-get-decls modi))
	   (modsubdecls (verilog-modi-get-sub-decls modi))
	   (sig-list (verilog-signals-not-in
		      (verilog-subdecls-get-inouts modsubdecls)
		      (append (verilog-decls-get-outputs moddecls)
			      (verilog-decls-get-inouts moddecls)
			      (verilog-decls-get-inputs moddecls)
			      (verilog-subdecls-get-inputs modsubdecls)
			      (verilog-subdecls-get-outputs modsubdecls)))))
      (when regexp
	(setq sig-list (verilog-signals-matching-regexp
			sig-list regexp)))
      (setq sig-list (verilog-signals-not-matching-regexp
		      sig-list verilog-auto-inout-ignore-regexp))
      (verilog-forward-or-insert-line)
      (when v2k (verilog-repair-open-comma))
      (when sig-list
	(verilog-insert-indent "// Beginning of automatic inouts (from unused autoinst inouts)\n")
	(verilog-insert-definition modi sig-list "inout" indent-pt v2k)
	(verilog-insert-indent "// End of automatics\n"))
      (when v2k (verilog-repair-close-comma)))))