Function: verilog-insert-definition

verilog-insert-definition is a byte-compiled function defined in verilog-mode.el.gz.

Signature

(verilog-insert-definition MODI SIGS DIRECTION INDENT-PT V2K &optional DONT-SORT)

Documentation

Print out a definition for MODI's list of SIGS of the given DIRECTION, with appropriate INDENT-PT indentation. If V2K, use Verilog 2001 I/O format. Sort unless DONT-SORT. DIRECTION is normally wire/reg/output. When MODI is non-null, also add to modi-cache, for tracking.

Source Code

;; Defined in /usr/src/emacs/lisp/progmodes/verilog-mode.el.gz
(defun verilog-insert-definition (modi sigs direction indent-pt v2k &optional dont-sort)
  "Print out a definition for MODI's list of SIGS of the given DIRECTION,
with appropriate INDENT-PT indentation.  If V2K, use Verilog 2001 I/O
format.  Sort unless DONT-SORT.  DIRECTION is normally wire/reg/output.
When MODI is non-null, also add to modi-cache, for tracking."
  (when modi
    (cond ((equal direction "wire")
	   (verilog-modi-cache-add-vars modi sigs))
	  ((equal direction "reg")
	   (verilog-modi-cache-add-vars modi sigs))
	  ((equal direction "output")
	   (verilog-modi-cache-add-outputs modi sigs)
	   (when verilog-auto-declare-nettype
	     (verilog-modi-cache-add-vars modi sigs)))
	  ((equal direction "input")
	   (verilog-modi-cache-add-inputs modi sigs)
	   (when verilog-auto-declare-nettype
	     (verilog-modi-cache-add-vars modi sigs)))
	  ((equal direction "inout")
	   (verilog-modi-cache-add-inouts modi sigs)
	   (when verilog-auto-declare-nettype
	     (verilog-modi-cache-add-vars modi sigs)))
	  ((equal direction "interface"))
	  ((equal direction "parameter")
	   (verilog-modi-cache-add-gparams modi sigs))
	  (t
	   (error "Unsupported verilog-insert-definition direction: `%s'" direction))))
  (or dont-sort
      (setq sigs (sort (copy-alist sigs) #'verilog-signals-sort-compare)))
  (while sigs
    (let ((sig (car sigs)))
      (verilog-insert-one-definition
       sig
       ;; Want "type x" or "output type x", not "wire type x"
       (cond ((and (equal "wire" verilog-auto-wire-type)
                   (or (not (verilog-sig-type sig))
                       (equal "logic" (verilog-sig-type sig))))
              (if (member direction '("input" "output" "inout"))
                  direction
                "wire"))
             ;;
             ((or (verilog-sig-type sig)
		  verilog-auto-wire-type)
	      (concat
	       (when (member direction '("input" "output" "inout"))
		 (concat direction " "))
               (or (verilog-sig-type sig)
                   verilog-auto-wire-type)))
             ;;
	     ((and verilog-auto-declare-nettype
		   (member direction '("input" "output" "inout")))
	      (concat direction " " verilog-auto-declare-nettype))
	     (t
	      direction))
       indent-pt)
      (insert (if v2k "," ";"))
      (if (or (not verilog-auto-wire-comment)
              (not (verilog-sig-comment sig))
              (equal "" (verilog-sig-comment sig)))
	  (insert "\n")
	(indent-to (max 48 (+ indent-pt 40)))
	(verilog-insert "// " (verilog-sig-comment sig) "\n"))
      (setq sigs (cdr sigs)))))