Function: verilog-read-sub-decls-expr

verilog-read-sub-decls-expr is a byte-compiled function defined in verilog-mode.el.gz.

Signature

(verilog-read-sub-decls-expr SUBMODDECLS PAR-VALUES COMMENT PORT EXPR)

Documentation

For verilog-read-sub-decls-line, parse a subexpression and add signals.

Source Code

;; Defined in /usr/src/emacs/lisp/progmodes/verilog-mode.el.gz
(defun verilog-read-sub-decls-expr (submoddecls par-values comment port expr)
  "For `verilog-read-sub-decls-line', parse a subexpression and add signals."
  ;;(message "vrsde: `%s'" expr)
  ;; Replace special /*[....]*/ comments inserted by verilog-auto-inst-port
  (setq expr (verilog-string-replace-matches
              "/\\*\\(\\.?\\[\\([^*]+\\|[*][^/]\\)+\\]\\)\\*/" "\\1" nil nil expr))
  ;; Remove front operators
  (setq expr (verilog-string-replace-matches "^\\s-*[---+~!|&]+\\s-*" "" nil nil expr))
  ;;
  (cond
   ;; {..., a, b} requires us to recurse on a,b
   ;; To support {#{},{#{a,b}} we'll just split everything on [{},]
   ((string-match "^\\s-*'?{\\(.*\\)}\\s-*$" expr)
    (let ((mlst (split-string (match-string 1 expr) "[{},]"))
          mstr)
      (while (setq mstr (pop mlst))
        (verilog-read-sub-decls-expr submoddecls par-values comment port mstr))))
   (t
    (let (sig vec multidim mem)
      ;; Remove leading reduction operators, etc
      (setq expr (verilog-string-replace-matches "^\\s-*[---+~!|&]+\\s-*" "" nil nil expr))
      ;; Remove casting types
      (setq expr (verilog-string-replace-matches
                  "^\\s-*[a-zA-Z_][a-zA-Z_0-9]*\\s-*'" "" nil nil expr))
      ;; Remove simple single set of parens (perhaps from cast, or perhaps not)
      (setq expr (verilog-string-replace-matches
                  "^\\s-*(\\([^)]*\\))\\s-*$" "\\1" nil nil expr))
      ;;(message "vrsde-ptop: `%s'" expr)
      (cond  ; Find \signal. Final space is part of escaped signal name
       ((string-match "^\\s-*\\(\\\\[^ \t\n\f]+\\s-\\)" expr)
	;;(message "vrsde-s: `%s'" (match-string 1 expr))
	(setq sig (match-string 1 expr)
	      expr (substring expr (match-end 0))))
       ;; Find signal
       ((string-match "^\\s-*\\([a-zA-Z_][a-zA-Z_0-9]*\\)" expr)
	;;(message "vrsde-s: `%s'" (match-string 1 expr))
	(setq sig (verilog-string-remove-spaces (match-string 1 expr))
	      expr (substring expr (match-end 0)))))
      ;; Find [vector] or [multi][multi][multi][vector] or [vector[VEC2]]
      ;; Unfortunately Emacs regexps don't allow matching bracket searches, so just 2 deep.
      (while (string-match "^\\s-*\\(\\[\\([^][]+\\|\\[[^][]+\\]\\)*\\]\\)" expr)
	;;(message "vrsde-v: `%s'" (match-string 1 expr))
	(when vec (setq multidim (cons vec multidim)))
	(setq vec (match-string 1 expr)
	      expr (substring expr (match-end 0))))
      ;; Find .[unpacked_memory] or .[unpacked][unpacked]...
      (while (string-match "^\\s-*\\.\\(\\(\\[[^]]+\\]\\)+\\)" expr)
	;;(message "vrsde-m: `%s'" (match-string 1 expr))
	(setq mem (match-string 1 expr)
	      expr (substring expr (match-end 0))))
      ;; If found signal, and nothing unrecognized, add the signal
      ;;(message "vrsde-rem: `%s'" expr)
      (when (and sig (string-match "^\\s-*$" expr))
        (verilog-read-sub-decls-sig submoddecls par-values comment port sig vec multidim mem))))))