Function: vhdl-template-process
vhdl-template-process is an interactive and byte-compiled function
defined in vhdl-mode.el.gz.
Signature
(vhdl-template-process &optional KIND)
Documentation
Insert a process.
Key Bindings
Source Code
;; Defined in /usr/src/emacs/lisp/progmodes/vhdl-mode.el.gz
(defun vhdl-template-process (&optional kind)
"Insert a process."
(interactive)
(let ((margin (current-indentation))
(start (point))
(reset-kind vhdl-reset-kind)
label seq input-signals clock reset final-pos)
(setq seq (if kind (eq kind 'seq)
(eq (vhdl-decision-query
"process" "(c)ombinational or (s)equential?" t) ?s)))
(vhdl-insert-keyword "PROCESS ")
(when (memq vhdl-optional-labels '(process all))
(goto-char start)
(insert ": ")
(goto-char start)
(setq label (vhdl-template-field "[label]" nil t))
(unless label (delete-char 2))
(forward-word-strictly 1)
(forward-char 1))
(insert "(")
(if (not seq)
(unless (or (and (vhdl-standard-p '08) vhdl-sensitivity-list-all
(progn (insert "all)") (setq input-signals "all")))
(setq input-signals
(vhdl-template-field "[sensitivity list]" ")" t)))
(setq input-signals "")
(delete-char -2))
(setq clock (or (and (not (equal "" vhdl-clock-name))
(progn (insert vhdl-clock-name) vhdl-clock-name))
(vhdl-template-field "clock name") "<clock>"))
(when (eq reset-kind 'query)
(setq reset-kind
(if (eq (vhdl-decision-query
"" "(a)synchronous or (s)ynchronous reset?" t) ?a)
'async
'sync)))
(when (eq reset-kind 'async)
(insert ", ")
(setq reset (or (and (not (equal "" vhdl-reset-name))
(progn (insert vhdl-reset-name) vhdl-reset-name))
(vhdl-template-field "reset name") "<reset>")))
(insert ")"))
(unless (vhdl-standard-p '87) (vhdl-insert-keyword " IS"))
(insert "\n")
(vhdl-template-begin-end "PROCESS" label margin)
(when seq (setq reset (vhdl-template-seq-process clock reset reset-kind)))
(when vhdl-prompt-for-comments
(setq final-pos (point-marker))
(vhdl-prepare-search-2
(when (and (vhdl-re-search-backward "\\<begin\\>" nil t)
(vhdl-re-search-backward "\\<process\\>" nil t))
(end-of-line -0)
(if (bobp)
(progn (insert "\n") (forward-line -1))
(insert "\n"))
(indent-to margin)
(insert "-- purpose: ")
(if (not (vhdl-template-field "[description]" nil t))
(vhdl-line-kill-entire)
(insert "\n")
(indent-to margin)
(insert "-- type : ")
(insert (if seq "sequential" "combinational") "\n")
(indent-to margin)
(insert "-- inputs : ")
(if (not seq)
(insert input-signals)
(insert clock ", ")
(when reset (insert reset ", "))
(unless (vhdl-template-field "[signal names]" nil t)
(delete-char -2)))
(insert "\n")
(indent-to margin)
(insert "-- outputs: ")
(vhdl-template-field "[signal names]" nil t))))
(goto-char final-pos))))