Variable: verilog-auto-lineup

verilog-auto-lineup is a customizable variable defined in verilog-mode.el.gz.

Value

declarations

Documentation

Type of statements to lineup across multiple lines.

If all is selected, then all line ups described below are done.

If declarations, then just declarations are lined up with any preceding declarations, taking into account widths and the like, so or example the code:
        reg [31:0] a;
        reg b;
would become
        reg [31:0] a;
        reg b;

If assignment, then assignments are lined up with any preceding assignments, so for example the code
        a_long_variable <= b + c;
        d = e + f;
would become
        a_long_variable <= b + c;
        d = e + f;

In order to speed up editing, large blocks of statements are lined up only when a M-x verilog-pretty-expr (verilog-pretty-expr) is typed; and large blocks of declarations are lineup only when M-x verilog-pretty-declarations (verilog-pretty-declarations) is typed.

Source Code

;; Defined in /usr/src/emacs/lisp/progmodes/verilog-mode.el.gz
(defcustom verilog-auto-lineup 'declarations
  "Type of statements to lineup across multiple lines.
If `all' is selected, then all line ups described below are done.

If `declarations', then just declarations are lined up with any
preceding declarations, taking into account widths and the like,
so or example the code:
        reg [31:0] a;
        reg b;
would become
        reg [31:0] a;
        reg        b;

If `assignment', then assignments are lined up with any preceding
assignments, so for example the code
        a_long_variable <= b + c;
        d = e + f;
would become
        a_long_variable <= b + c;
        d                = e + f;

In order to speed up editing, large blocks of statements are lined up
only when a \\[verilog-pretty-expr] is typed; and large blocks of declarations
are lineup only when \\[verilog-pretty-declarations] is typed."

  :type '(radio (const :tag "Line up Assignments and Declarations" all)
		(const :tag "Line up Assignment statements" assignments )
		(const :tag "Line up Declarations" declarations)
		(function :tag "Other"))
  :group 'verilog-mode-indent )