Variable: verilog-keywords

verilog-keywords is a variable defined in verilog-mode.el.gz.

Value

("`__FILE__" "`__LINE" "`begin_keywords" "`celldefine"
 "`default_nettype" "`define" "`else" "`elsif" "`end_keywords"
 "`endcelldefine" "`endif" "`ifdef" "`ifndef" "`include" "`line"
 "`nounconnected_drive" "`pragma" "`resetall" "`timescale"
 "`unconnected_drive" "`undef" "`undefineall" "`case" "`default"
 "`endfor" "`endprotect" "`endswitch" "`endwhile" "`for" "`format"
 "`if" "`let" "`protect" "`switch" "`time_scale" "`uselib" "`while"
 "after" "alias" "always" "always_comb" "always_ff" "always_latch"
 "analog" "and" "assert" "assign" "assume" "automatic" "before"
 "begin" "bind" "bins" "binsof" "bit" "break" "buf" "bufif0" "bufif1"
 "byte" "case" "casex" "casez" "cell" "chandle" "class" "clocking"
 "cmos" "config" "const" "constraint" "context" "continue" "cover"
 "covergroup" "coverpoint" "cross" "deassign" "default" "defparam"
 "design" "disable" "dist" "do" "edge" "else" "end" "endcase"
 "endclass" "endclocking" "endconfig" "endfunction" "endgenerate"
 "endgroup" "endinterface" "endmodule" "endpackage" "endprimitive"
 "endprogram" "endproperty" "endspecify" "endsequence" "endtable"
 "endtask" "enum" "event" "expect" "export" "extends" "extern" "final"
 "first_match" "for" "force" "foreach" "forever" "fork" "forkjoin"
 "function" "generate" "genvar" "highz0" "highz1" "if" "iff" "ifnone"
 "ignore_bins" "illegal_bins" "import" "incdir" "include" "initial"
 "inout" "input" "inside" "instance" "int" "integer" "interface"
 "intersect" "join" "join_any" "join_none" "large" "liblist" "library"
 "local" "localparam" "logic" "longint" "macromodule" "mailbox"
 "matches" "medium" "modport" "module" "nand" "negedge" "new" "nmos"
 "nor" "noshowcancelled" "not" "notif0" "notif1" "null" "or" "output"
 "package" "packed" "parameter" "pmos" "posedge" "primitive"
 "priority" "program" "property" "protected" "pull0" "pull1"
 "pulldown" "pullup" "pulsestyle_onevent" "pulsestyle_ondetect" "pure"
 "rand" "randc" "randcase" "randsequence" "rcmos" "real" "realtime"
 "ref" "reg" "release" "repeat" "return" "rnmos" "rpmos" "rtran"
 "rtranif0" "rtranif1" "scalared" "semaphore" "sequence" "shortint"
 "shortreal" "showcancelled" "signed" "small" "solve" "specify"
 "specparam" "static" "string" "strong0" "strong1" "struct" "super"
 "supply0" "supply1" "table" "tagged" "task" "this" "throughout"
 "time" "timeprecision" "timeunit" "tran" "tranif0" "tranif1" "tri"
 "tri0" "tri1" "triand" "trior" "trireg" "type" "typedef" "union"
 "unique" "unsigned" "use" "uwire" "var" "vectored" "virtual" "void"
 "wait" "wait_order" "wand" "weak0" "weak1" "while" "wildcard" "wire"
 "with" "within" "wor" "xnor" "xor" "accept_on" "checker" "endchecker"
 "eventually" "global" "implies" "let" "nexttime" "reject_on"
 "restrict" "s_always" "s_eventually" "s_nexttime" "s_until"
 "s_until_with" "strong" "sync_accept_on" "sync_reject_on" "unique0"
 "until" "until_with" "untyped" "weak" "implements" "interconnect"
 "nettype" "soft" "connectmodule" "endconnectmodule")

Documentation

List of Verilog keywords.

Source Code

;; Defined in /usr/src/emacs/lisp/progmodes/verilog-mode.el.gz
(defconst verilog-keywords
  (append verilog-compiler-directives
          '(
            "after" "alias" "always" "always_comb" "always_ff" "always_latch" "analog" "and"
            "assert" "assign" "assume" "automatic" "before" "begin" "bind"
            "bins" "binsof" "bit" "break" "buf" "bufif0" "bufif1" "byte"
            "case" "casex" "casez" "cell" "chandle" "class" "clocking" "cmos"
            "config" "const" "constraint" "context" "continue" "cover"
            "covergroup" "coverpoint" "cross" "deassign" "default" "defparam"
            "design" "disable" "dist" "do" "edge" "else" "end" "endcase"
            "endclass" "endclocking" "endconfig" "endfunction" "endgenerate"
            "endgroup" "endinterface" "endmodule" "endpackage" "endprimitive"
            "endprogram" "endproperty" "endspecify" "endsequence" "endtable"
            "endtask" "enum" "event" "expect" "export" "extends" "extern"
            "final" "first_match" "for" "force" "foreach" "forever" "fork"
            "forkjoin" "function" "generate" "genvar" "highz0" "highz1" "if"
            "iff" "ifnone" "ignore_bins" "illegal_bins" "import" "incdir"
            "include" "initial" "inout" "input" "inside" "instance" "int"
            "integer" "interface" "intersect" "join" "join_any" "join_none"
            "large" "liblist" "library" "local" "localparam" "logic"
            "longint" "macromodule" "mailbox" "matches" "medium" "modport" "module"
            "nand" "negedge" "new" "nmos" "nor" "noshowcancelled" "not"
            "notif0" "notif1" "null" "or" "output" "package" "packed"
            "parameter" "pmos" "posedge" "primitive" "priority" "program"
            "property" "protected" "pull0" "pull1" "pulldown" "pullup"
            "pulsestyle_onevent" "pulsestyle_ondetect" "pure" "rand" "randc"
            "randcase" "randsequence" "rcmos" "real" "realtime" "ref" "reg"
            "release" "repeat" "return" "rnmos" "rpmos" "rtran" "rtranif0"
            "rtranif1" "scalared" "semaphore" "sequence" "shortint" "shortreal"
            "showcancelled" "signed" "small" "solve" "specify" "specparam"
            "static" "string" "strong0" "strong1" "struct" "super" "supply0"
            "supply1" "table" "tagged" "task" "this" "throughout" "time"
            "timeprecision" "timeunit" "tran" "tranif0" "tranif1" "tri"
            "tri0" "tri1" "triand" "trior" "trireg" "type" "typedef" "union"
            "unique" "unsigned" "use" "uwire" "var" "vectored" "virtual" "void"
            "wait" "wait_order" "wand" "weak0" "weak1" "while" "wildcard"
            "wire" "with" "within" "wor" "xnor" "xor"
            ;; 1800-2009
            "accept_on" "checker" "endchecker" "eventually" "global" "implies"
            "let" "nexttime" "reject_on" "restrict" "s_always" "s_eventually"
            "s_nexttime" "s_until" "s_until_with" "strong" "sync_accept_on"
            "sync_reject_on" "unique0" "until" "until_with" "untyped" "weak"
            ;; 1800-2012
            "implements" "interconnect" "nettype" "soft"
            ;; AMS
            "connectmodule" "endconnectmodule"
            ))
  "List of Verilog keywords.")