Variable: verilog-stmt-menu

verilog-stmt-menu is a variable defined in verilog-mode.el.gz.

Value

<nil-15>  nil
<nil-22>  nil
<nil-8>   nil
<nil>     nil

Documentation

Menu for statement templates in Verilog.

Key Bindings

Source Code

;; Defined in /usr/src/emacs/lisp/progmodes/verilog-mode.el.gz
(easy-menu-define
  verilog-stmt-menu verilog-mode-map "Menu for statement templates in Verilog."
  (verilog-easy-menu-filter
   '("Statements"
     ["Header"		verilog-sk-header
      :help		"Insert a header block at the top of file"]
     ["Comment"		verilog-sk-comment
      :help		"Insert a comment block"]
     "----"
     ["Module"		verilog-sk-module
      :help		"Insert a module .. (/*AUTOARG*/);.. endmodule block"]
     ["OVM Class"	verilog-sk-ovm-class
      :help		"Insert an OVM class block"]
     ["UVM Object"	verilog-sk-uvm-object
      :help		"Insert an UVM object block"]
     ["UVM Component"	verilog-sk-uvm-component
      :help		"Insert an UVM component block"]
     ["Primitive"	verilog-sk-primitive
      :help		"Insert a primitive .. (.. );.. endprimitive block"]
     "----"
     ["Input"		verilog-sk-input
      :help		"Insert an input declaration"]
     ["Output"		verilog-sk-output
      :help		"Insert an output declaration"]
     ["Inout"		verilog-sk-inout
      :help		"Insert an inout declaration"]
     ["Wire"		verilog-sk-wire
      :help		"Insert a wire declaration"]
     ["Reg"		verilog-sk-reg
      :help		"Insert a register declaration"]
     ["Define thing under point as a register" verilog-sk-define-signal
      :help		"Define signal under point as a register at the top of the module"]
     "----"
     ["Initial"		verilog-sk-initial
      :help		"Insert an initial begin .. end block"]
     ["Always"		verilog-sk-always
      :help		"Insert an always @(AS) begin .. end block"]
     ["Function"	verilog-sk-function
      :help		"Insert a function .. begin .. end endfunction block"]
     ["Task"		verilog-sk-task
      :help		"Insert a task .. begin .. end endtask block"]
     ["Specify"		verilog-sk-specify
      :help		"Insert a specify .. endspecify block"]
     ["Generate"	verilog-sk-generate
      :help		"Insert a generate .. endgenerate block"]
     "----"
     ["Begin"		verilog-sk-begin
      :help		"Insert a begin .. end block"]
     ["If"		verilog-sk-if
      :help		"Insert an if (..) begin .. end block"]
     ["(if) else"	verilog-sk-else-if
      :help		"Insert an else if (..) begin .. end block"]
     ["For"		verilog-sk-for
      :help		"Insert a for (...) begin .. end block"]
     ["While"		verilog-sk-while
      :help		"Insert a while (...) begin .. end block"]
     ["Fork"		verilog-sk-fork
      :help		"Insert a fork begin .. end .. join block"]
     ["Repeat"		verilog-sk-repeat
      :help		"Insert a repeat (..) begin .. end block"]
     ["Case"		verilog-sk-case
      :help		"Insert a case block, prompting for details"]
     ["Casex"		verilog-sk-casex
      :help		"Insert a casex (...) item: begin.. end endcase block"]
     ["Casez"		verilog-sk-casez
      :help		"Insert a casez (...) item: begin.. end endcase block"])))