Variable: vhdl-testbench-statements

vhdl-testbench-statements is a customizable variable defined in vhdl-mode.el.gz.

Value

"  -- clock generation\n  Clk <= not Clk after 10 ns;\n\n  -- waveform generation\n  WaveGen_Proc: process\n  begin\n    -- insert signal assignments here\n\n    wait until Clk = '1';\n  end process WaveGen_Proc;\n"

Documentation

String or file to be inserted in the testbench statement part.

If the string specifies an existing file name, the contents of the file is inserted, otherwise the string itself is inserted in the testbench architecture before the END keyword. Type C-j for newlines.

Source Code

;; Defined in /usr/src/emacs/lisp/progmodes/vhdl-mode.el.gz
(defcustom vhdl-testbench-statements "\
  -- clock generation
  Clk <= not Clk after 10 ns;

  -- waveform generation
  WaveGen_Proc: process
  begin
    -- insert signal assignments here

    wait until Clk = '1';
  end process WaveGen_Proc;
"
  "String or file to be inserted in the testbench statement part.
If the string specifies an existing file name, the contents of the file is
inserted, otherwise the string itself is inserted in the testbench
architecture before the END keyword.
Type `C-j' for newlines."
  :type 'string
  :group 'vhdl-testbench)