Variable: vhdl-verilog-keywords

vhdl-verilog-keywords is a variable defined in vhdl-mode.el.gz.

Value

("`define" "`else" "`endif" "`ifdef" "`include" "`timescale" "`undef"
 "always" "and" "assign" "begin" "buf" "bufif0" "bufif1" "case"
 "casex" "casez" "cmos" "deassign" "default" "defparam" "disable"
 "edge" "else" "end" "endattribute" "endcase" "endfunction"
 "endmodule" "endprimitive" "endspecify" "endtable" "endtask" "event"
 "for" "force" "forever" "fork" "function" "highz0" "highz1" "if"
 "initial" "inout" "input" "integer" "join" "large" "macromodule"
 "makefile" "medium" "module" "nand" "negedge" "nmos" "nor" "not"
 "notif0" "notif1" "or" "output" "parameter" "pmos" "posedge"
 "primitive" "pull0" "pull1" "pulldown" "pullup" "rcmos" "real"
 "realtime" "reg" "release" "repeat" "rnmos" "rpmos" "rtran"
 "rtranif0" "rtranif1" "scalared" "signed" "small" "specify"
 "specparam" "strength" "strong0" "strong1" "supply" "supply0"
 "supply1" "table" "task" "time" "tran" "tranif0" "tranif1" "tri"
 "tri0" "tri1" "triand" "trior" "trireg" "vectored" "wait" "wand"
 "weak0" "weak1" "while" "wire" "wor" "xnor" "xor")

Documentation

List of Verilog keywords as candidate for additional reserved words.

Source Code

;; Defined in /usr/src/emacs/lisp/progmodes/vhdl-mode.el.gz
(defconst vhdl-verilog-keywords
  '(
    "`define" "`else" "`endif" "`ifdef" "`include" "`timescale" "`undef"
    "always" "and" "assign" "begin" "buf" "bufif0" "bufif1"
    "case" "casex" "casez" "cmos" "deassign" "default" "defparam" "disable"
    "edge" "else" "end" "endattribute" "endcase" "endfunction" "endmodule"
    "endprimitive" "endspecify" "endtable" "endtask" "event"
    "for" "force" "forever" "fork" "function"
    "highz0" "highz1" "if" "initial" "inout" "input" "integer" "join" "large"
    "macromodule" "makefile" "medium" "module"
    "nand" "negedge" "nmos" "nor" "not" "notif0" "notif1" "or" "output"
    "parameter" "pmos" "posedge" "primitive" "pull0" "pull1" "pulldown"
    "pullup"
    "rcmos" "real" "realtime" "reg" "release" "repeat" "rnmos" "rpmos" "rtran"
    "rtranif0" "rtranif1"
    "scalared" "signed" "small" "specify" "specparam" "strength" "strong0"
    "strong1" "supply" "supply0" "supply1"
    "table" "task" "time" "tran" "tranif0" "tranif1" "tri" "tri0" "tri1"
    "triand" "trior" "trireg"
    "vectored" "wait" "wand" "weak0" "weak1" "while" "wire" "wor" "xnor" "xor"
    )
  "List of Verilog keywords as candidate for additional reserved words.")