Function: `verilog-auto-inout-in`

verilog-auto-inout-in is a byte-compiled function defined in verilog-mode.el.gz.

Signature

(verilog-auto-inout-in)

Documentation

Expand AUTOINOUTIN statements, as part of M-x verilog-auto (verilog-auto).

Take input/output/inout statements from the specified module and insert them as all inputs into the current module. This is useful for making monitor modules which need to see all signals as inputs based on another module. Any I/O which are already defined in this module will not be redefined. See also verilog-auto-inout-module.

Limitations:
If placed inside the parenthesis of a module declaration, it creates
Verilog 2001 style, else uses Verilog 1995 style.

Concatenation and outputting partial buses is not supported.

Module names must be resolvable to filenames. See verilog-auto-inst.

  Signals are not inserted in the same order as in the original module,
  though they will appear to be in the same order to an AUTOINST
  instantiating either module.

An example:

        module ExampMain
          (input i,
           output o,
           inout io);
        endmodule

        module ExampInoutIn (/*AUTOARG*/);
           /*AUTOINOUTIN("ExampMain")*/
        endmodule

Typing M-x verilog-auto (verilog-auto) will make this into:

        module ExampInoutIn (/*AUTOARG*/i, io, o);
           /*AUTOINOUTIN("ExampMain")*/
           // Beginning of automatic in/out/inouts
           input i;
           input io;
           input o;
           // End of automatics
        endmodule

You may also provide an optional regular expression, in which case only signals matching the regular expression will be included, or excluded if the regexp begins with ?! (question-mark exclamation-mark). For example the same expansion will result from only extracting signals starting with i:

/*AUTOINOUTIN("ExampMain","^i")*/

Source Code

;; Defined in /usr/src/emacs/lisp/progmodes/verilog-mode.el.gz
(defun verilog-auto-inout-in ()
  "Expand AUTOINOUTIN statements, as part of \\[verilog-auto].
Take input/output/inout statements from the specified module and
insert them as all inputs into the current module.  This is
useful for making monitor modules which need to see all signals
as inputs based on another module.  Any I/O which are already
defined in this module will not be redefined.  See also
`verilog-auto-inout-module'.

Limitations:
  If placed inside the parenthesis of a module declaration, it creates
  Verilog 2001 style, else uses Verilog 1995 style.

  Concatenation and outputting partial buses is not supported.

  Module names must be resolvable to filenames.  See `verilog-auto-inst'.

  Signals are not inserted in the same order as in the original module,
  though they will appear to be in the same order to an AUTOINST
  instantiating either module.

An example:

        module ExampMain
          (input i,
           output o,
           inout io);
        endmodule

        module ExampInoutIn (/*AUTOARG*/);
           /*AUTOINOUTIN(\"ExampMain\")*/
        endmodule

Typing \\[verilog-auto] will make this into:

        module ExampInoutIn (/*AUTOARG*/i, io, o);
           /*AUTOINOUTIN(\"ExampMain\")*/
           // Beginning of automatic in/out/inouts
           input i;
           input io;
           input o;
           // End of automatics
        endmodule

You may also provide an optional regular expression, in which
case only signals matching the regular expression will be
included, or excluded if the regexp begins with ?! (question-mark
exclamation-mark).  For example the same expansion will result
from only extracting signals starting with i:

           /*AUTOINOUTIN(\"ExampMain\",\"^i\")*/"
  (verilog-auto-inout-module nil t))

Function: verilog-auto-inout-in

Signature

Documentation

Source Code

Function: `verilog-auto-inout-in`