Function: verilog-auto-inout-module

verilog-auto-inout-module is a byte-compiled function defined in verilog-mode.el.gz.

Signature

(verilog-auto-inout-module &optional COMPLEMENT ALL-IN)

Documentation

Expand AUTOINOUTMODULE statements, as part of M-x verilog-auto (verilog-auto).

Take input/output/inout statements from the specified module and insert into the current module. This is useful for making null templates and shell modules which need to have identical I/O with another module. Any I/O which are already defined in this module will not be redefined. For the complement of this function, see verilog-auto-inout-comp, and to make monitors with all inputs, see verilog-auto-inout-in.

Limitations:
  If placed inside the parenthesis of a module declaration, it creates
  Verilog 2001 style, else uses Verilog 1995 style.

  Concatenation and outputting partial buses is not supported.

  Module names must be resolvable to filenames. See verilog-auto-inst.

  Signals are not inserted in the same order as in the original module,
  though they will appear to be in the same order to an AUTOINST
  instantiating either module.

  Signals declared as "output reg" or "output wire" etc will
  lose the wire/reg declaration so that shell modules may
  generate those outputs differently. However, "output logic"
  is propagated.

An example:

        module ExampMain
          (input i,
           output o,
           inout io);
        endmodule

        module ExampShell (/*AUTOARG*/);
           /*AUTOINOUTMODULE("ExampMain")*/
        endmodule

Typing M-x verilog-auto (verilog-auto) will make this into:

        module ExampShell (/*AUTOARG*/o, io, o);
           /*AUTOINOUTMODULE("ExampMain")*/
           // Beginning of automatic in/out/inouts
           output o;
           inout io;
           input i;
           // End of automatics
        endmodule

You may also provide an optional regular expression, in which case only signals matching the regular expression will be included, or excluded if the regexp begins with ?! (question-mark exclamation-mark). For example the same expansion will result from only extracting signals starting with i:

           /*AUTOINOUTMODULE("ExampMain","^i")*/

You may also provide an optional third argument regular expression, in which case only signals which have that pin direction and data type matching that regular expression will be included. This matches against everything before the signal name in the declaration, for example against "input" (single bit), "output logic" (direction and type) or
"output [1:0]" (direction and implicit type). You also
probably want to skip spaces in your regexp.

For example, the below will result in matching the output "o" against the previous example's module:

           /*AUTOINOUTMODULE("ExampMain","","^output.*")*/

You may also provide an optional fourth argument regular expression, which if not "" only signals which do NOT match that expression are included.

Source Code

;; Defined in /usr/src/emacs/lisp/progmodes/verilog-mode.el.gz
(defun verilog-auto-inout-module (&optional complement all-in)
  "Expand AUTOINOUTMODULE statements, as part of \\[verilog-auto].
Take input/output/inout statements from the specified module and insert
into the current module.  This is useful for making null templates and
shell modules which need to have identical I/O with another module.
Any I/O which are already defined in this module will not be redefined.
For the complement of this function, see `verilog-auto-inout-comp',
and to make monitors with all inputs, see `verilog-auto-inout-in'.

Limitations:
  If placed inside the parenthesis of a module declaration, it creates
  Verilog 2001 style, else uses Verilog 1995 style.

  Concatenation and outputting partial buses is not supported.

  Module names must be resolvable to filenames.  See `verilog-auto-inst'.

  Signals are not inserted in the same order as in the original module,
  though they will appear to be in the same order to an AUTOINST
  instantiating either module.

  Signals declared as \"output reg\" or \"output wire\" etc will
  lose the wire/reg declaration so that shell modules may
  generate those outputs differently.  However, \"output logic\"
  is propagated.

An example:

        module ExampMain
          (input i,
           output o,
           inout io);
        endmodule

        module ExampShell (/*AUTOARG*/);
           /*AUTOINOUTMODULE(\"ExampMain\")*/
        endmodule

Typing \\[verilog-auto] will make this into:

        module ExampShell (/*AUTOARG*/o, io, o);
           /*AUTOINOUTMODULE(\"ExampMain\")*/
           // Beginning of automatic in/out/inouts
           output o;
           inout io;
           input i;
           // End of automatics
        endmodule

You may also provide an optional regular expression, in which
case only signals matching the regular expression will be
included, or excluded if the regexp begins with ?! (question-mark
exclamation-mark).  For example the same expansion will result
from only extracting signals starting with i:

           /*AUTOINOUTMODULE(\"ExampMain\",\"^i\")*/

You may also provide an optional third argument regular
expression, in which case only signals which have that pin
direction and data type matching that regular expression will be
included.  This matches against everything before the signal name
in the declaration, for example against \"input\" (single
bit), \"output logic\" (direction and type) or
\"output [1:0]\" (direction and implicit type).  You also
probably want to skip spaces in your regexp.

For example, the below will result in matching the output \"o\"
against the previous example's module:

           /*AUTOINOUTMODULE(\"ExampMain\",\"\",\"^output.*\")*/

You may also provide an optional fourth argument regular
expression, which if not \"\" only signals which do NOT match
that expression are included."
  ;; Beware spacing of quotes in above as can mess up Emacs indenter
  (save-excursion
    (let* ((params (verilog-read-auto-params 1 4))
	   (submod (nth 0 params))
	   (regexp (nth 1 params))
	   (direction-re (nth 2 params))
	   (not-re (nth 3 params))
	   submodi)
      ;; Lookup position, etc of co-module
      ;; Note this may raise an error
      (when (setq submodi (verilog-modi-lookup submod t))
	(let* ((indent-pt (current-indentation))
	       (v2k  (verilog-in-paren-quick))
	       (modi (verilog-modi-current))
	       (moddecls (verilog-modi-get-decls modi))
	       (submoddecls (verilog-modi-get-decls submodi))
	       (sig-list-i  (verilog-signals-not-in
			     (cond (all-in
				    (append
				     (verilog-decls-get-inputs submoddecls)
				     (verilog-decls-get-inouts submoddecls)
				     (verilog-decls-get-outputs submoddecls)))
				   (complement
				    (verilog-decls-get-outputs submoddecls))
				   (t (verilog-decls-get-inputs submoddecls)))
			     (append (verilog-decls-get-inputs moddecls))))
	       (sig-list-o  (verilog-signals-not-in
			     (cond (all-in nil)
				   (complement
				    (verilog-decls-get-inputs submoddecls))
				   (t (verilog-decls-get-outputs submoddecls)))
			     (append (verilog-decls-get-outputs moddecls))))
	       (sig-list-io (verilog-signals-not-in
			     (cond (all-in nil)
				   (t (verilog-decls-get-inouts submoddecls)))
			     (append (verilog-decls-get-inouts moddecls))))
	       (sig-list-if (verilog-signals-not-in
			     (verilog-decls-get-interfaces submoddecls)
			     (append (verilog-decls-get-interfaces moddecls)))))
	  (forward-line 1)
	  (setq sig-list-i  (verilog-signals-edit-wire-reg
			     (verilog-signals-not-matching-regexp
			      (verilog-signals-matching-dir-re
			       (verilog-signals-matching-regexp sig-list-i regexp)
                              "input" direction-re)
                             not-re))
		sig-list-o  (verilog-signals-edit-wire-reg
			     (verilog-signals-not-matching-regexp
			      (verilog-signals-matching-dir-re
			       (verilog-signals-matching-regexp sig-list-o regexp)
                              "output" direction-re)
                             not-re))
		sig-list-io (verilog-signals-edit-wire-reg
			     (verilog-signals-not-matching-regexp
			      (verilog-signals-matching-dir-re
			       (verilog-signals-matching-regexp sig-list-io regexp)
                              "inout" direction-re)
                             not-re))
		sig-list-if (verilog-signals-not-matching-regexp
			     (verilog-signals-matching-dir-re
			      (verilog-signals-matching-regexp sig-list-if regexp)
                             "interface" direction-re)
                            not-re))
	  (when v2k (verilog-repair-open-comma))
	  (when (or sig-list-i sig-list-o sig-list-io sig-list-if)
	    (verilog-insert-indent "// Beginning of automatic in/out/inouts (from specific module)\n")
	    ;; Don't sort them so an upper AUTOINST will match the main module
	    (verilog-insert-definition modi sig-list-o  "output" indent-pt v2k t)
	    (verilog-insert-definition modi sig-list-io "inout" indent-pt v2k t)
	    (verilog-insert-definition modi sig-list-i  "input" indent-pt v2k t)
	    (verilog-insert-definition modi sig-list-if "interface" indent-pt v2k t)
	    (verilog-insert-indent "// End of automatics\n"))
	  (when v2k (verilog-repair-close-comma)))))))