Variable: verilog-auto-inst-param-value
verilog-auto-inst-param-value is a customizable variable defined in
verilog-mode.el.gz.
Value
nil
Documentation
Non-nil means AUTOINST will replace parameters with the parameter value.
If nil, leave parameters as symbolic names.
Parameters must be in Verilog 2001 format #(...), and if a parameter is not listed as such there (as when the default value is acceptable), it will not be replaced, and will remain symbolic.
For example, imagine a submodule uses parameters to declare the size of its inputs. This is then used by an upper module:
module InstModule (o,i);
parameter WIDTH;
input [WIDTH-1:0] i;
parameter type OUT_t;
output OUT_t o;
endmodule
module ExampParamVal1;
/*AUTOOUTPUT*/
// Beginning of automatic outputs
output OUT_t o;
// End of automatics
InstModule
#(.WIDTH(10),
,.OUT_t(upper_t))
instName
(/*AUTOINST*/
.o (o),
.i (i[WIDTH-1:0]));
endmodule
// Local Variables:
// verilog-typedef-regexp: "_t$"
// End:
Note even though WIDTH=10, the AUTOINST has left the parameter as a symbolic name. Likewise the OUT_t is preserved as the name from the instantiated module.
If verilog-auto-inst-param-value is set, this will
instead expand to:
module ExampParamVal1;
/*AUTOOUTPUT*/
// Beginning of automatic outputs
output upper_t o;
// End of automatics
InstModule
#(.WIDTH(10),
,.OUT_t(upper_t))
instName
(/*AUTOINST*/
.o (o),
.i (i[9:0]));
Note that the instantiation now has "i[9:0]" as the WIDTH
was expanded. Likewise the data type of "o" in the AUTOOUTPUT
is now upper_t, from the OUT_t parameter override.
This second expansion of parameter types can be overridden with
verilog-auto-inst-param-value-type.
Source Code
;; Defined in /usr/src/emacs/lisp/progmodes/verilog-mode.el.gz
(defcustom verilog-auto-inst-param-value nil
"Non-nil means AUTOINST will replace parameters with the parameter value.
If nil, leave parameters as symbolic names.
Parameters must be in Verilog 2001 format #(...), and if a parameter is not
listed as such there (as when the default value is acceptable), it will not
be replaced, and will remain symbolic.
For example, imagine a submodule uses parameters to declare the size of its
inputs. This is then used by an upper module:
module InstModule (o,i);
parameter WIDTH;
input [WIDTH-1:0] i;
parameter type OUT_t;
output OUT_t o;
endmodule
module ExampParamVal1;
/*AUTOOUTPUT*/
// Beginning of automatic outputs
output OUT_t o;
// End of automatics
InstModule
#(.WIDTH(10),
,.OUT_t(upper_t))
instName
(/*AUTOINST*/
.o (o),
.i (i[WIDTH-1:0]));
endmodule
// Local Variables:
// verilog-typedef-regexp: \"_t$\"
// End:
Note even though WIDTH=10, the AUTOINST has left the parameter as
a symbolic name. Likewise the OUT_t is preserved as the name
from the instantiated module.
If `verilog-auto-inst-param-value' is set, this will
instead expand to:
module ExampParamVal1;
/*AUTOOUTPUT*/
// Beginning of automatic outputs
output upper_t o;
// End of automatics
InstModule
#(.WIDTH(10),
,.OUT_t(upper_t))
instName
(/*AUTOINST*/
.o (o),
.i (i[9:0]));
Note that the instantiation now has \"i[9:0]\" as the WIDTH
was expanded. Likewise the data type of \"o\" in the AUTOOUTPUT
is now upper_t, from the OUT_t parameter override.
This second expansion of parameter types can be overridden with
`verilog-auto-inst-param-value-type'."
:group 'verilog-mode-auto
:type 'boolean)