Function: verilog-inject-auto

verilog-inject-auto is an interactive and byte-compiled function defined in verilog-mode.el.gz.

Signature

(verilog-inject-auto)

Documentation

Examine legacy non-AUTO code and insert AUTOs in appropriate places.

Any always @ blocks with sensitivity lists that match computed lists will be replaced with /*AS*/ comments.

Any cells will get /*AUTOINST*/ added to the end of the pin list. Pins with have identical names will be deleted.

Argument lists will not be deleted, /*AUTOARG*/ will only be inserted to support adding new ports. You may wish to delete older ports yourself.

For example:

        module ExampInject (i, o);
          input i;
          input j;
          output o;
          always @ (i or j)
             o = i | j;
          InstModule instName
            (.foobar(baz),
             .j(j));
        endmodule

Typing M-x verilog-inject-auto (verilog-inject-auto) (with an appropriate submodule not shown) will make this into:

        module ExampInject (i, o/*AUTOARG*/
          // Inputs
          j);
          input i;
          output o;
          always @ (/*AS*/i or j)
             o = i | j;
          InstModule instName
            (.foobar(baz),
             /*AUTOINST*/
             // Outputs
             j(j));
        endmodule

Key Bindings

Source Code

;; Defined in /usr/src/emacs/lisp/progmodes/verilog-mode.el.gz
;;; Auto inject:
;;

(defun verilog-inject-auto ()
  "Examine legacy non-AUTO code and insert AUTOs in appropriate places.

Any always @ blocks with sensitivity lists that match computed lists will
be replaced with /*AS*/ comments.

Any cells will get /*AUTOINST*/ added to the end of the pin list.
Pins with have identical names will be deleted.

Argument lists will not be deleted, /*AUTOARG*/ will only be inserted to
support adding new ports.  You may wish to delete older ports yourself.

For example:

        module ExampInject (i, o);
          input i;
          input j;
          output o;
          always @ (i or j)
             o = i | j;
          InstModule instName
            (.foobar(baz),
             .j(j));
        endmodule

Typing \\[verilog-inject-auto] (with an appropriate submodule not
shown) will make this into:

        module ExampInject (i, o/*AUTOARG*/
          // Inputs
          j);
          input i;
          output o;
          always @ (/*AS*/i or j)
             o = i | j;
          InstModule instName
            (.foobar(baz),
             /*AUTOINST*/
             // Outputs
             j(j));
        endmodule"
  (interactive)
  (verilog-auto t))