Function: verilog-auto-inst-port
verilog-auto-inst-port is a byte-compiled function defined in
verilog-mode.el.gz.
Signature
(verilog-auto-inst-port SECTION PORT-ST INDENT-PT MODDECLS TPL-LIST TPL-NUM FOR-STAR PAR-VALUES)
Documentation
Print out an instantiation connection for this PORT-ST.
Inside SECTION, insert to INDENT-PT, use template TPL-LIST.
@ are instantiation numbers, replaced with TPL-NUM.
@"(expression @)" are evaluated, with @ as a variable.
If FOR-STAR add comment it is a .* expansion.
If PAR-VALUES replace final strings with these parameter values.
Source Code
;; Defined in /usr/src/emacs/lisp/progmodes/verilog-mode.el.gz
(defvar vl-mbits nil "See `verilog-auto-inst'.") ; Prevent compile warning
(defun verilog-auto-inst-port (section port-st indent-pt moddecls tpl-list tpl-num
for-star par-values)
"Print out an instantiation connection for this PORT-ST.
Inside SECTION, insert to INDENT-PT, use template TPL-LIST.
@ are instantiation numbers, replaced with TPL-NUM.
@\"(expression @)\" are evaluated, with @ as a variable.
If FOR-STAR add comment it is a .* expansion.
If PAR-VALUES replace final strings with these parameter values."
(let* ((port (verilog-sig-name port-st))
(tpl-ass (or (assoc port (car tpl-list))
(verilog-auto-inst-port-map port-st)))
;; vl-* are documented for user use
(vl-name (verilog-sig-name port-st))
(vl-width (verilog-sig-width port-st))
(vl-modport (verilog-sig-modport port-st))
(vl-memory (verilog-sig-memory port-st))
(vl-mbits (if (verilog-sig-multidim port-st)
(verilog-sig-multidim-string port-st) ""))
(vl-bits (or (verilog-sig-bits port-st) ""))
(case-fold-search nil)
(check-values par-values)
auto-inst-vector
auto-inst-vector-tpl
tpl-net dflt-bits)
;; Replace parameters in bit-width
(when (and check-values
(not (equal vl-bits "")))
(while check-values
(setq vl-bits (verilog-string-replace-matches
(concat "\\<" (nth 0 (car check-values)) "\\>")
(concat "(" (nth 1 (car check-values)) ")")
t t vl-bits)
vl-mbits (verilog-string-replace-matches
(concat "\\<" (nth 0 (car check-values)) "\\>")
(concat "(" (nth 1 (car check-values)) ")")
t t vl-mbits)
vl-memory (when vl-memory
(verilog-string-replace-matches
(concat "\\<" (nth 0 (car check-values)) "\\>")
(concat "(" (nth 1 (car check-values)) ")")
t t vl-memory))
check-values (cdr check-values)))
(setq vl-bits (verilog-simplify-range-expression vl-bits)
vl-mbits (verilog-simplify-range-expression vl-mbits)
vl-memory (when vl-memory (verilog-simplify-range-expression vl-memory))
vl-width (verilog-make-width-expression vl-bits))) ; Not in the loop for speed
(setq auto-inst-vector
(if (or (eq verilog-auto-inst-vector t)
(and (eq verilog-auto-inst-vector `unsigned)
(not (verilog-sig-signed port-st)))
(not (assoc port (verilog-decls-get-signals moddecls)))
(not (equal (verilog-sig-bits port-st)
(verilog-sig-bits
(assoc port (verilog-decls-get-signals moddecls))))))
vl-bits
""))
;; Default net value if not found
(setq dflt-bits (if (or (and (verilog-sig-bits port-st)
(verilog-sig-multidim port-st))
(verilog-sig-memory port-st))
(concat "/*" vl-mbits vl-bits
;; .[ used to separate packed from unpacked
(if vl-memory "." "")
(if vl-memory vl-memory "")
"*/")
(concat auto-inst-vector))
tpl-net (concat port
(if (and vl-modport
;; .modport cannot be added if attachment is
;; already declared as modport, VCS croaks
(let ((sig (assoc port (verilog-decls-get-interfaces moddecls))))
(not (and sig (verilog-sig-modport sig)))))
(concat "." vl-modport) "")
dflt-bits))
;; Find template
(cond (tpl-ass ; Template of exact port name
(setq tpl-net (nth 1 tpl-ass)))
((nth 1 tpl-list) ; Wildcards in template, search them
(let ((wildcards (nth 1 tpl-list)))
(while wildcards
(when (string-match (nth 0 (car wildcards)) port)
(setq tpl-ass (car wildcards) ; so allow @ parsing
tpl-net (replace-match (nth 1 (car wildcards))
t nil port)))
(setq wildcards (cdr wildcards))))))
;; Parse Templated variable
(when tpl-ass
;; Evaluate @"(lispcode)"
(when (string-match "@\".*[^\\]\"" tpl-net)
(while (string-match "@\"\\(\\([^\\\"]\\|\\\\.\\)*\\)\"" tpl-net)
(setq tpl-net
(concat
(substring tpl-net 0 (match-beginning 0))
(save-match-data
(let* ((expr (match-string 1 tpl-net))
(value
(progn
(setq expr (verilog-string-replace-matches "\\\\\"" "\"" nil nil expr))
(setq expr (verilog-string-replace-matches "@" tpl-num nil nil expr))
(prin1 (eval (car (read-from-string expr)))
(lambda (_ch) ())))))
(if (numberp value) (setq value (number-to-string value)))
value))
(substring tpl-net (match-end 0))))))
;; Get range based off template net
(setq auto-inst-vector-tpl
(if (or (eq verilog-auto-inst-vector t)
(and (eq verilog-auto-inst-vector `unsigned)
(not (verilog-sig-signed port-st)))
(not (assoc tpl-net (verilog-decls-get-signals moddecls)))
(not (equal (verilog-sig-bits port-st)
(verilog-sig-bits
(assoc tpl-net (verilog-decls-get-signals moddecls))))))
vl-bits
""))
;; Replace @ and [] magic variables in final output
(setq tpl-net (verilog-string-replace-matches "@" tpl-num nil nil tpl-net))
(setq tpl-net (verilog-string-replace-matches "\\[\\]\\[\\]" dflt-bits nil nil tpl-net))
(setq tpl-net (verilog-string-replace-matches "\\[\\]" auto-inst-vector-tpl nil nil tpl-net)))
;; Insert it
(when (or tpl-ass (not verilog-auto-inst-template-required))
(verilog--auto-inst-first indent-pt section)
(indent-to indent-pt)
(insert "." port)
(unless (and verilog-auto-inst-dot-name
(equal port tpl-net))
(indent-to verilog-auto-inst-column)
(insert "(" tpl-net ")"))
(insert ",")
(cond (tpl-ass
(verilog-read-auto-template-hit tpl-ass)
(indent-to (+ (if (< verilog-auto-inst-column 48) 24 16)
verilog-auto-inst-column))
;; verilog-insert requires the complete comment in one call - including the newline
(cond ((equal verilog-auto-inst-template-numbers 'lhs)
(verilog-insert " // Templated"
" LHS: " (nth 0 tpl-ass)))
(verilog-auto-inst-template-numbers
(verilog-insert " // Templated"
" T" (int-to-string (nth 2 tpl-ass))
" L" (int-to-string (nth 3 tpl-ass))))
(t
(verilog-insert " // Templated")))
(verilog-insert (if (nth 4 tpl-ass) " AUTONOHOOKUP\n" "\n")))
(for-star
(indent-to (+ (if (< verilog-auto-inst-column 48) 24 16)
verilog-auto-inst-column))
(verilog-insert " // Implicit .*\n"))
(t
(insert "\n"))))))