Function: verilog-auto-output

verilog-auto-output is a byte-compiled function defined in verilog-mode.el.gz.

Signature

(verilog-auto-output)

Documentation

Expand AUTOOUTPUT statements, as part of M-x verilog-auto (verilog-auto).

Make output statements for any output signal from an /*AUTOINST*/ that isn't an input to another AUTOINST. This is useful for modules which only instantiate other modules.

Limitations:
  This ONLY detects outputs of AUTOINSTants (see verilog-read-sub-decls).

  If placed inside the parenthesis of a module declaration, it creates
  Verilog 2001 style, else uses Verilog 1995 style.

  If any concatenation, or bit-subscripts are missing in the AUTOINSTant's
  instantiation, all bets are off. (For example due to an AUTO_TEMPLATE).

  Typedefs must match verilog-typedef-regexp, which is disabled by default.

  Types are added to declarations if an AUTOLOGIC or
  verilog-auto-wire-type is set to logic.

  Signals matching verilog-auto-output-ignore-regexp are not included.

An example (see verilog-auto-inst for what else is going on here):

        module InstModule (output o);
        endmodule

        module ExampOutput
           (/*AUTOOUTPUT*/
           );
           InstModule instName
             (/*AUTOINST*/);
        endmodule

Typing M-x verilog-auto (verilog-auto) will make this into:

        module ExampOutput
          (/*AUTOOUTPUT*/
           // Beginning of automatic outputs
           output o // From instName of InstModule.v
           // End of automatics
           );
          InstModule instName
            (/*AUTOINST*/
             // Outputs
             .o (o));
        endmodule

You may also provide an optional regular expression, in which case only signals matching the regular expression will be included. For example the same expansion will result from only extracting outputs starting with ov:

           /*AUTOOUTPUT("^ov")*/

Source Code

;; Defined in /usr/src/emacs/lisp/progmodes/verilog-mode.el.gz
(defun verilog-auto-output ()
  "Expand AUTOOUTPUT statements, as part of \\[verilog-auto].
Make output statements for any output signal from an /*AUTOINST*/ that
isn't an input to another AUTOINST.  This is useful for modules which
only instantiate other modules.

Limitations:
  This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').

  If placed inside the parenthesis of a module declaration, it creates
  Verilog 2001 style, else uses Verilog 1995 style.

  If any concatenation, or bit-subscripts are missing in the AUTOINSTant's
  instantiation, all bets are off.  (For example due to an AUTO_TEMPLATE).

  Typedefs must match `verilog-typedef-regexp', which is disabled by default.

  Types are added to declarations if an AUTOLOGIC or
  `verilog-auto-wire-type' is set to logic.

  Signals matching `verilog-auto-output-ignore-regexp' are not included.

An example (see `verilog-auto-inst' for what else is going on here):

        module InstModule (output o);
        endmodule

        module ExampOutput
           (/*AUTOOUTPUT*/
           );
           InstModule instName
             (/*AUTOINST*/);
        endmodule

Typing \\[verilog-auto] will make this into:

        module ExampOutput
          (/*AUTOOUTPUT*/
           // Beginning of automatic outputs
           output          o    // From instName of InstModule.v
           // End of automatics
           );
          InstModule instName
            (/*AUTOINST*/
             // Outputs
             .o          (o));
        endmodule

You may also provide an optional regular expression, in which case only
signals matching the regular expression will be included.  For example the
same expansion will result from only extracting outputs starting with ov:

           /*AUTOOUTPUT(\"^ov\")*/"
  (save-excursion
    ;; Point must be at insertion point.
    (let* ((indent-pt (current-indentation))
	   (params (verilog-read-auto-params 0 1))
	   (regexp (nth 0 params))
	   (v2k  (verilog-in-paren-quick))
	   (modi (verilog-modi-current))
	   (moddecls (verilog-modi-get-decls modi))
	   (modsubdecls (verilog-modi-get-sub-decls modi))
	   (sig-list (verilog-signals-not-in
		      (verilog-subdecls-get-outputs modsubdecls)
		      (append (verilog-decls-get-outputs moddecls)
			      (verilog-decls-get-inouts moddecls)
			      (verilog-decls-get-inputs moddecls)
			      (verilog-subdecls-get-inputs modsubdecls)
			      (verilog-subdecls-get-inouts modsubdecls)))))
      (when regexp
	(setq sig-list (verilog-signals-matching-regexp
			sig-list regexp)))
      (setq sig-list (verilog-signals-not-matching-regexp
		      sig-list verilog-auto-output-ignore-regexp))
      (verilog-forward-or-insert-line)
      (when v2k (verilog-repair-open-comma))
      (when sig-list
	(verilog-insert-indent "// Beginning of automatic outputs (from unused autoinst outputs)\n")
	(verilog-insert-definition modi sig-list "output" indent-pt v2k)
	(verilog-insert-indent "// End of automatics\n"))
      (when v2k (verilog-repair-close-comma)))))