Function: verilog-auto-reg-input

verilog-auto-reg-input is a byte-compiled function defined in verilog-mode.el.gz.

Signature

(verilog-auto-reg-input)

Documentation

Expand AUTOREGINPUT statements, as part of M-x verilog-auto (verilog-auto).

Make reg statements instantiation inputs that aren't already declared or assigned to. This is useful for making a top level shell for testing the module that is to be instantiated.

Limitations:
  This ONLY detects inputs of AUTOINSTants (see verilog-read-sub-decls).

  This does NOT work on memories, declare those yourself.

  Assignments cause the assigned-to variable not to be declared unless
  the name matches verilog-auto-reg-input-assigned-ignore-regexp.

An example (see verilog-auto-inst for what else is going on here):

        module InstModule (input i);
        endmodule

        module ExampRegInput ();
           /*AUTOREGINPUT*/
           InstModule instName
             (/*AUTOINST*/);
        endmodule

Typing M-x verilog-auto (verilog-auto) will make this into:

        module ExampRegInput ();
           /*AUTOREGINPUT*/
           // Beginning of automatic reg inputs
           reg i; // To instName of InstModule.v
           // End of automatics
           InstModule instName
             (/*AUTOINST*/
              // Inputs
              .i (i));
        endmodule

Source Code

;; Defined in /usr/src/emacs/lisp/progmodes/verilog-mode.el.gz
(defun verilog-auto-reg-input ()
  "Expand AUTOREGINPUT statements, as part of \\[verilog-auto].
Make reg statements instantiation inputs that aren't already
declared or assigned to.  This is useful for making a top level
shell for testing the module that is to be instantiated.

Limitations:
  This ONLY detects inputs of AUTOINSTants (see `verilog-read-sub-decls').

  This does NOT work on memories, declare those yourself.

  Assignments cause the assigned-to variable not to be declared unless
  the name matches `verilog-auto-reg-input-assigned-ignore-regexp'.

An example (see `verilog-auto-inst' for what else is going on here):

        module InstModule (input i);
        endmodule

        module ExampRegInput ();
           /*AUTOREGINPUT*/
           InstModule instName
             (/*AUTOINST*/);
        endmodule

Typing \\[verilog-auto] will make this into:

        module ExampRegInput ();
           /*AUTOREGINPUT*/
           // Beginning of automatic reg inputs
           reg          i;      // To instName of InstModule.v
           // End of automatics
           InstModule instName
             (/*AUTOINST*/
              // Inputs
              .i                (i));
        endmodule"
  (save-excursion
    ;; Point must be at insertion point.
    (let* ((indent-pt (current-indentation))
	   (modi (verilog-modi-current))
	   (moddecls (verilog-modi-get-decls modi))
	   (modsubdecls (verilog-modi-get-sub-decls modi))
	   (sig-list (verilog-signals-combine-bus
		      (verilog-signals-not-in
		       (append (verilog-subdecls-get-inputs modsubdecls)
			       (verilog-subdecls-get-inouts modsubdecls))
		       (append (verilog-decls-get-signals moddecls)
                               (verilog-signals-not-matching-regexp
                                (verilog-decls-get-assigns moddecls)
                                verilog-auto-reg-input-assigned-ignore-regexp))))))
      (when sig-list
	(verilog-forward-or-insert-line)
	(verilog-insert-indent "// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)\n")
	(verilog-insert-definition modi sig-list "reg" indent-pt nil)
	(verilog-insert-indent "// End of automatics\n")))))