Function: verilog-read-includes
verilog-read-includes is a byte-compiled function defined in
verilog-mode.el.gz.
Signature
(verilog-read-includes)
Documentation
Read `includes for the current file.
This will find all of the `includes which are at the beginning of lines,
ignoring any ifdefs or multiline comments around them.
verilog-read-defines is then performed on the current and each included
file.
It is often useful put at the *END* of your file something like:
// Local Variables:
// verilog-auto-read-includes:t
// End:
Or the equivalent longer version, which requires having
enable-local-eval non-nil:
// Local Variables:
// eval:(verilog-read-defines)
// eval:(verilog-read-includes)
// End:
Note includes are only read when the file is first visited, you must use
C-x C-v (find-alternate-file) RET to have these take effect after editing them!
It is good to get in the habit of including all needed files in each .v file that needs it, rather than waiting for compile time. This will aid this process, Verilint, and readability. To prevent defining the same variable over and over when many modules are compiled together, put a test around the inside each include file:
foo.v (an include file):
`ifndef _FOO_V // include if not already included
`define _FOO_V
... contents of file
`endif // _FOO_V
Source Code
;; Defined in /usr/src/emacs/lisp/progmodes/verilog-mode.el.gz
(defun verilog-read-includes ()
"Read \\=`includes for the current file.
This will find all of the \\=`includes which are at the beginning of lines,
ignoring any ifdefs or multiline comments around them.
`verilog-read-defines' is then performed on the current and each included
file.
It is often useful put at the *END* of your file something like:
// Local Variables:
// verilog-auto-read-includes:t
// End:
Or the equivalent longer version, which requires having
`enable-local-eval' non-nil:
// Local Variables:
// eval:(verilog-read-defines)
// eval:(verilog-read-includes)
// End:
Note includes are only read when the file is first visited, you must use
\\[find-alternate-file] RET to have these take effect after editing them!
It is good to get in the habit of including all needed files in each .v
file that needs it, rather than waiting for compile time. This will aid
this process, Verilint, and readability. To prevent defining the same
variable over and over when many modules are compiled together, put a test
around the inside each include file:
foo.v (an include file):
\\=`ifndef _FOO_V // include if not already included
\\=`define _FOO_V
... contents of file
\\=`endif // _FOO_V"
;;slow: (verilog-read-defines nil t)
(save-excursion
(verilog-getopt-flags)
(goto-char (point-min))
(while (re-search-forward "^\\s-*`include\\s-+\\([^ \t\n\f]+\\)" nil t)
(let ((inc (verilog-substitute-include-name
(match-string-no-properties 1))))
(verilog-read-defines inc nil t)))))