Function: verilog-set-auto-endcomments

verilog-set-auto-endcomments is a byte-compiled function defined in verilog-mode.el.gz.

Signature

(verilog-set-auto-endcomments INDENT-STR KILL-EXISTING-COMMENT)

Documentation

Add ending comment with given INDENT-STR.

With KILL-EXISTING-COMMENT, remove what was there before.
Insert // case: 7 or // NAME on this line if appropriate.
Insert // case expr if this line ends a case block.
Insert // ifdef FOO if this line ends code conditional on FOO.
Insert // NAME if this line ends a function, task, module,
primitive or interface named NAME.

Source Code

;; Defined in /usr/src/emacs/lisp/progmodes/verilog-mode.el.gz
(defun verilog-set-auto-endcomments (indent-str kill-existing-comment)
  "Add ending comment with given INDENT-STR.
With KILL-EXISTING-COMMENT, remove what was there before.
Insert `// case: 7 ' or `// NAME ' on this line if appropriate.
Insert `// case expr ' if this line ends a case block.
Insert `// ifdef FOO ' if this line ends code conditional on FOO.
Insert `// NAME ' if this line ends a function, task, module,
primitive or interface named NAME."
  (save-excursion
    (cond
     (; Comment close preprocessor directives
      (and
       (looking-at "\\(`endif\\)\\|\\(`else\\)")
       (or  kill-existing-comment
	    (not (save-excursion
		   (end-of-line)
                   (search-backward "//" (line-beginning-position) t)))))
      (let ((nest 1) b e
	    m
	    (else (if (match-end 2) "!" " ")))
	(end-of-line)
	(if kill-existing-comment
	    (verilog-kill-existing-comment))
	(delete-horizontal-space)
	(save-excursion
	  (backward-sexp 1)
	  (while (and (/= nest 0)
		      (verilog-re-search-backward verilog-directive-nest-re nil 'move))
	    (cond
	     ((match-end 1) ; `else
	      (if (= nest 1)
		  (setq else "!")))
	     ((match-end 2) ; `endif
	      (setq nest (1+ nest)))
	     ((match-end 3) ; `if
	      (setq nest (1- nest)))
	     ((match-end 4) ; `ifdef
	      (setq nest (1- nest)))
	     ((match-end 5) ; `ifndef
	      (setq nest (1- nest)))
	     ((match-end 6) ; `elsif
	      (if (= nest 1)
		  (progn
		    (setq else "!")
		    (setq nest 0))))))
	  (if (match-end 0)
	      (setq
	       m (buffer-substring
		  (match-beginning 0)
		  (match-end 0))
	       b (progn
		   (skip-chars-forward "^ \t")
		   (verilog-forward-syntactic-ws)
		   (point))
	       e (progn
		   (skip-chars-forward "a-zA-Z0-9_")
		   (point)))))
	(if b
	    (if (> (count-lines (point) b) verilog-minimum-comment-distance)
		(insert (concat " // " else m " " (buffer-substring b e))))
	  (progn
	    (insert " // unmatched `else, `elsif or `endif")
	    (ding 't)))))

     (; Comment close case/class/function/task/module and named block
      (and (looking-at "\\<end")
	   (or kill-existing-comment
	       (not (save-excursion
		      (end-of-line)
                      (search-backward "//" (line-beginning-position) t)))))
      (let ((type (car indent-str)))
	(unless (eq type 'declaration)
          (unless (looking-at (concat "\\(" verilog-end-block-ordered-re "\\)[ \t]*:"))  ; ignore named ends
	    (if (looking-at verilog-end-block-ordered-re)
                (cond
                 (;- This is a case block; search back for the start of this case
                  (match-end 1)  ; of verilog-end-block-ordered-re

                  (let ((err 't)
                        (str "UNMATCHED!!"))
                    (save-excursion
                      (verilog-leap-to-head)
                      (cond
                       ((looking-at "\\<randcase\\>")
                        (setq str "randcase")
                        (setq err nil))
                       ((looking-at "\\(\\(unique0?\\s-+\\|priority\\s-+\\)?case[xz]?\\)")
                        (goto-char (match-end 0))
                        (setq str (concat (match-string 0) " " (verilog-get-expr)))
                        (setq err nil))
                       ))
                    (end-of-line)
                    (if kill-existing-comment
                        (verilog-kill-existing-comment))
                    (delete-horizontal-space)
                    (insert (concat " // " str ))
                    (if err (ding 't))))

                 (;- This is a begin..end block
                  (match-end 2)  ; of verilog-end-block-ordered-re
                  (let ((str " // UNMATCHED !!")
                        (err 't)
                        (here (point))
                        there
                        cntx)
                    (save-excursion
                      (verilog-leap-to-head)
                      (setq there (point))
                      (if (not (match-end 0))
                          (progn
                            (goto-char here)
                            (end-of-line)
                            (if kill-existing-comment
                                (verilog-kill-existing-comment))
                            (delete-horizontal-space)
                            (insert str)
                            (ding 't))
                        (let ((lim
                               (save-excursion (verilog-re-search-backward verilog-defun-re nil 'move) (point)))
                              (here (point)))
                          (cond
                           (;-- handle named block differently
                            (looking-at verilog-named-block-re)
                            (search-forward ":")
                            (setq there (point))
                            (setq str (verilog-get-expr))
                            (setq err nil)
                            (setq str (concat " // block: " str )))

                           ((verilog-in-case-region-p) ;-- handle case item differently
                            (goto-char here)
                            (setq str (verilog-backward-case-item lim))
                            (setq there (point))
                            (setq err nil)
                            (setq str (concat " // case: " str )))

                           (;- try to find "reason" for this begin
                            (cond
                             (;
                              (eq here (progn
                                         ;;   (verilog-backward-token)
                                         (verilog-beg-of-statement)
                                         (point)))
                              (setq err nil)
                              (setq str ""))
                             ((looking-at verilog-endcomment-reason-re)
                              (setq there (match-end 0))
                              (setq cntx (concat (match-string 0) " "))
                              (cond
                               (;- begin
                                (match-end 1)
                                (setq err nil)
                                (save-excursion
                                  (if (and (verilog-continued-line)
                                           (looking-at "\\<repeat\\>\\|\\<wait\\>\\|\\<always\\>"))
                                      (progn
                                        (goto-char (match-end 0))
                                        (setq there (point))
                                        (setq str
                                              (concat " // " (match-string 0) " " (verilog-get-expr))))
                                    (setq str ""))))

                               (;- else
                                (match-end 2)
                                (let ((nest 0)
                                      ( reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|\\(\\<if\\>\\)\\|\\(assert\\)"))
                                  (catch 'skip
                                    (while (verilog-re-search-backward reg nil 'move)
                                      (cond
                                       ((match-end 1) ; begin
                                        (setq nest (1- nest)))
                                       ((match-end 2)                       ; end
                                        (setq nest (1+ nest)))
                                       ((match-end 3)
                                        (if (= 0 nest)
                                            (progn
                                              (goto-char (match-end 0))
                                              (setq there (point))
                                              (setq err nil)
                                              (setq str (verilog-get-expr))
                                              (setq str (concat " // else: !if" str ))
                                              (throw 'skip 1))))
                                       ((match-end 4)
                                        (if (= 0 nest)
                                            (progn
                                              (goto-char (match-end 0))
                                              (setq there (point))
                                              (setq err nil)
                                              (setq str (verilog-get-expr))
                                              (setq str (concat " // else: !assert " str ))
                                              (throw 'skip 1)))))))))
                               (;- end else
                                (match-end 3)
                                (goto-char there)
                                (let ((nest 0)
                                      (reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|\\(\\<if\\>\\)\\|\\(\\<assert\\>\\)"))
                                  (catch 'skip
                                    (while (verilog-re-search-backward reg nil 'move)
                                      (cond
                                       ((match-end 1) ; begin
                                        (setq nest (1- nest)))
                                       ((match-end 2)                       ; end
                                        (setq nest (1+ nest)))
                                       ((match-end 3)
                                        (if (= 0 nest)
                                            (progn
                                              (goto-char (match-end 0))
                                              (setq there (point))
                                              (setq err nil)
                                              (setq str (verilog-get-expr))
                                              (setq str (concat " // else: !if" str ))
                                              (throw 'skip 1))))
                                       ((match-end 4)
                                        (if (= 0 nest)
                                            (progn
                                              (goto-char (match-end 0))
                                              (setq there (point))
                                              (setq err nil)
                                              (setq str (verilog-get-expr))
                                              (setq str (concat " // else: !assert " str ))
                                              (throw 'skip 1)))))))))

                               (; always, always_comb, always_latch w/o @...
                                (or (match-end 5) (match-end 6))
                                (goto-char (match-end 0))
                                (setq there (point))
                                (setq err nil)
                                (setq str (concat " // " cntx )))

                               (;- task/function/initial et cetera
                                t
                                (goto-char (match-end 0))
                                (setq there (point))
                                (setq err nil)
                                (setq str (concat " // " cntx (verilog-get-expr))))))

                             ((and
                               (verilog-in-case-region-p) ;-- handle case item differently
                               (progn
                                 (setq there (point))
                                 (goto-char here)
                                 (setq str (verilog-backward-case-item lim))))
                              (setq err nil)
                              (setq str (concat " // case: " str )))

                             ((verilog-in-fork-region-p)
                              (setq err nil)
                              (setq str " // fork branch" ))

                             ((looking-at "\\<end\\>")
                              ;; HERE
                              (forward-word-strictly 1)
                              (verilog-forward-syntactic-ws)
                              (setq err nil)
                              (setq str (verilog-get-expr))
                              (setq str (concat " // " cntx str )))

                             ))))
                        (goto-char here)
                        (end-of-line)
                        (if kill-existing-comment
                            (verilog-kill-existing-comment))
                        (delete-horizontal-space)
                        (if (or err
                                (> (count-lines here there) verilog-minimum-comment-distance))
                            (insert str))
                        (if err (ding 't))
                        ))))
                 (;- this is endclass, which can be nested
                  (match-end 11)  ; of verilog-end-block-ordered-re
                  ;;(goto-char there)
                  (let ((nest 0)
                        (reg "\\<\\(\\(class\\)\\|\\(endclass\\)\\|\\(package\\|primitive\\|\\(macro\\)?module\\)\\)\\>")
                        string)
                    (save-excursion
                      (catch 'skip
                        (while (verilog-re-search-backward reg nil 'move)
                          (cond
                           ((match-end 4)       ; endclass
                            (ding 't)
                            (setq string "unmatched endclass")
                            (throw 'skip 1))

                           ((match-end 3)       ; endclass
                            (setq nest (1+ nest)))

                           ((match-end 2) ; class
                            (setq nest (1- nest))
                            (if (< nest 0)
                                (progn
                                  (goto-char (match-end 0))
                                  (let (b e)
                                    (setq b (progn
                                              (skip-chars-forward "^ \t")
                                              (verilog-forward-ws&directives)
                                              (point))
                                          e (progn
                                              (skip-chars-forward "a-zA-Z0-9_")
                                              (point)))
                                    (setq string (buffer-substring b e)))
                                  (throw 'skip 1))))
                           ))))
                    (end-of-line)
                    (if kill-existing-comment
                        (verilog-kill-existing-comment))
                    (delete-horizontal-space)
                    (insert (concat " // " string ))))

                 (;  - this is end{function,generate,task,module,primitive,table,generate}
                  ;; - which can not be nested.
                  t
                  (let (string reg (name-re nil))
                    (end-of-line)
                    (if kill-existing-comment
                        (save-match-data
                          (verilog-kill-existing-comment)))
                    (delete-horizontal-space)
                    (backward-sexp)
                    (cond
                     ((match-end 5)  ; of verilog-end-block-ordered-re
                      (setq reg "\\(\\<function\\>\\)\\|\\(\\<\\(endfunction\\|task\\|\\(macro\\)?module\\|primitive\\)\\>\\)")
                      (setq name-re "\\w+\\(?:\n\\|\\s-\\)*[(;]"))
                     ((match-end 6)  ; of verilog-end-block-ordered-re
                      (setq reg "\\(\\<task\\>\\)\\|\\(\\<\\(endtask\\|function\\|\\(macro\\)?module\\|primitive\\)\\>\\)")
                      (setq name-re "\\w+\\(?:\n\\|\\s-\\)*[(;]"))
                     ((match-end 7)  ; of verilog-end-block-ordered-re
                      (setq reg "\\(\\<\\(macro\\)?module\\>\\)\\|\\<endmodule\\>"))
                     ((match-end 8)  ; of verilog-end-block-ordered-re
                      (setq reg "\\(\\<primitive\\>\\)\\|\\(\\<\\(endprimitive\\|package\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
                     ((match-end 9)  ; of verilog-end-block-ordered-re
                      (setq reg "\\(\\<interface\\>\\)\\|\\(\\<\\(endinterface\\|package\\|primitive\\|\\(macro\\)?module\\)\\>\\)"))
                     ((match-end 10)  ; of verilog-end-block-ordered-re
                      (setq reg "\\(\\<package\\>\\)\\|\\(\\<\\(endpackage\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
                     ((match-end 11)  ; of verilog-end-block-ordered-re
                      (setq reg "\\(\\<class\\>\\)\\|\\(\\<\\(endclass\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
                     ((match-end 12)  ; of verilog-end-block-ordered-re
                      (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<\\(endcovergroup\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
                     ((match-end 13)  ; of verilog-end-block-ordered-re
                      (setq reg "\\(\\<program\\>\\)\\|\\(\\<\\(endprogram\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
                     ((match-end 14)  ; of verilog-end-block-ordered-re
                      (setq reg "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<\\(endsequence\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
                     ((match-end 15)  ; of verilog-end-block-ordered-re
                      (setq reg "\\(\\<clocking\\>\\)\\|\\<endclocking\\>"))
                     ((match-end 16)  ; of verilog-end-block-ordered-re
                      (setq reg "\\(\\<property\\>\\)\\|\\<endproperty\\>"))
                     ((match-end 17)  ; of verilog-end-block-ordered-re
                      (setq reg "\\(\\<connectmodule\\>\\)\\|\\<endconnectmodule\\>"))

                     (t (error "Problem in verilog-set-auto-endcomments")))
                    (let (b e)
                      (save-excursion
                        (verilog-re-search-backward reg nil 'move)
                        (cond
                         ((match-end 1)
                          (setq b (progn
                                    (skip-chars-forward "^ \t")
                                    (verilog-forward-ws&directives)
                                    (if (looking-at "static\\|automatic")
                                        (progn
                                          (goto-char (match-end 0))
                                          (verilog-forward-ws&directives)))
                                    (if (and name-re (verilog-re-search-forward name-re nil 'move))
                                        (progn
                                          (goto-char (match-beginning 0))
                                          (verilog-forward-ws&directives)))
                                    (point))
                                e (progn
                                    (skip-chars-forward "a-zA-Z0-9_")
                                    (point)))
                          (setq string (buffer-substring b e)))
                         (t
                          (ding 't)
                          (setq string "unmatched end(function|task|module|connectmodule|primitive|interface|package|class|clocking)")))))
                    (end-of-line)
                    (insert (concat " // " string )))
                  ))))))))))