File: vhdl-mode.el.html
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
This package provides an Emacs major mode for editing VHDL code. It includes the following features:
- Syntax highlighting
- Indentation
- Template insertion (electrification)
- Insertion of file headers
- Insertion of user-specified models
- Port translation / testbench generation
- Structural composition
- Configuration generation
- Sensitivity list updating
- File browser
- Design hierarchy browser
- Source file compilation (syntax analysis)
- Makefile generation
- Code hiding
- Word/keyword completion
- Block commenting
- Code fixing/alignment/beautification
- PostScript printing
- VHDL'87/'93/'02/'08 and VHDL-AMS supported
- Comprehensive menu
- Fully customizable
- Works under GNU Emacs (recommended) and XEmacs
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
Documentation
See comment string of function vhdl-mode or type C-c C-h in Emacs.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
Emacs Versions
this updated version was only tested on: GNU Emacs 24.1
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
Installation
Prerequisites: GNU Emacs >= 21, XEmacs 20/21.
Put vhdl-mode.el into the site-lisp directory of your Emacs installation
or into an arbitrary directory that is added to the load path by the
following line in your Emacs start-up file .emacs:
(push (expand-file-name "<directory-name>") load-path)
If you already have the compiled vhdl-mode.elc file, put it in the same
directory. Otherwise, byte-compile the source file:
Emacs: M-x byte-compile-file RET vhdl-mode.el RET
Unix: emacs -batch -q -no-site-file -f batch-byte-compile vhdl-mode.el
Add the following lines to the site-start.el file in the site-lisp
directory of your Emacs installation or to your Emacs start-up file .emacs
(not required in Emacs):
(autoload 'vhdl-mode "vhdl-mode" "VHDL Mode" t)
(push '("\\\\.vhdl?\\\\'" . vhdl-mode) auto-mode-alist)
More detailed installation instructions are included in the official VHDL Mode distribution.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
Acknowledgments
Electrification ideas by Bob Pack <rlpst@cislabs.pitt.edu> and Steve Grout.
Fontification approach suggested by Ken Wood <ken@eda.com.au>. Ideas about alignment from John Wiegley <johnw@gnu.org>.
Many thanks to all the users who sent me bug reports and enhancement requests. Thanks to Colin Marquardt for his serious beta testing, his innumerable enhancement suggestions and the fruitful discussions. Thanks to Dan Nicolaescu for reviewing the code and for his valuable hints. Thanks to Ulf Klaperski for the indentation speedup hint.
Special thanks go to Wolfgang Fichtner and the crew from the Integrated Systems Laboratory, Swiss Federal Institute of Technology Zurich, for giving me the opportunity to develop this code. This work has been funded in part by MICROSWISS, a Microelectronics Program of the Swiss Government.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
Defined variables (258)
vhdl--progress-reporter | Holds the progress reporter data during long running operations. |
vhdl--signal-regions-functions | Define syntactic regions where signals are read. |
vhdl-02-attributes | List of VHDL’02 standardized attributes. |
vhdl-02-enum-values | List of VHDL’02 standardized enumeration values. |
vhdl-02-functions | List of VHDL’02 standardized functions. |
vhdl-02-keywords | List of VHDL’02 keywords. |
vhdl-02-packages | List of VHDL’02 standardized packages and libraries. |
vhdl-02-types | List of VHDL’02 standardized types. |
vhdl-08-attributes | List of VHDL’08 standardized attributes. |
vhdl-08-directives | List of VHDL’08 standardized tool directives. |
vhdl-08-functions | List of VHDL’08 standardized functions. |
vhdl-08-keywords | List of VHDL’08 keywords. |
vhdl-08-packages | List of VHDL’08 standardized packages and libraries. |
vhdl-08-types | List of VHDL’08 standardized types. |
vhdl-abbrev-list | Predefined abbreviations for VHDL. |
vhdl-actual-generic-name | Specifies how actual generic names are obtained from formal generic names. |
vhdl-actual-port-name | Specifies how actual port names are obtained from formal port names. |
vhdl-align-alist | The format of this alist is (MODES [or MODE] REGEXP ALIGN-PATTERN SUBEXP). |
vhdl-align-group-separate | Regexp for matching a line that separates groups of lines for alignment. |
vhdl-align-groups | Non-nil means align groups of code lines separately. |
vhdl-align-same-indent | Non-nil means align blocks with same indent separately. |
vhdl-align-try-all-clauses | If REGEXP is not found on the first line of the region that clause is ignored. |
vhdl-ams-attributes | List of VHDL-AMS standardized attributes. |
vhdl-ams-constants | List of VHDL-AMS standardized constants. |
vhdl-ams-enum-values | List of VHDL-AMS standardized enumeration values. |
vhdl-ams-functions | List of VHDL-AMS standardized functions. |
vhdl-ams-keywords | List of VHDL-AMS keywords. |
vhdl-ams-packages | List of VHDL-AMS standardized packages and libraries. |
vhdl-ams-types | List of VHDL-AMS standardized types. |
vhdl-architecture-file-name | Specifies how the architecture file name is obtained. |
vhdl-argument-list-indent | Non-nil means indent argument lists relative to opening parenthesis. |
vhdl-array-index-record-field-in-sensitivity-list | Non-nil means include array indices / record fields in sensitivity list. |
vhdl-association-list-with-formals | Non-nil means write association lists with formal parameters. |
vhdl-attributes | List of VHDL standardized attributes. |
vhdl-attributes-regexp | Regexp for VHDL standardized attributes. |
vhdl-auto-align | Non-nil means align some templates automatically after generation. |
vhdl-basic-offset | Amount of basic offset used for indentation. |
vhdl-beautify-options | List of options for beautifying code. |
vhdl-begin-bwd-re | Regexp for searching backward that matches all known "begin" keywords. |
vhdl-begin-fwd-re | Regexp for searching forward that matches all known "begin" keywords. |
vhdl-case-alternative-re | Regexp describing a case statement alternative key. |
vhdl-case-header-key | Regexp describing a case statement header key. |
vhdl-clock-edge-condition | Syntax of the clock edge condition. |
vhdl-clock-name | Name of clock signal to use in templates. |
vhdl-clock-rising-edge | Non-nil means rising edge of clock triggers sequential processes. |
vhdl-comment-display-line-char | Character to use in comment display line. |
vhdl-comment-only-line-offset | Extra offset for line which contains only the start of a comment. |
vhdl-company-name | Name of company to insert in file header. |
vhdl-compile-absolute-path | If non-nil, use absolute instead of relative path for compiled files. |
vhdl-compile-file-name | Name of file to be compiled. |
vhdl-compile-post-command | String appended to compile command after file name. |
vhdl-compile-use-local-error-regexp | Non-nil means use buffer-local ‘compilation-error-regexp-alist’. |
vhdl-compiler | Specifies the VHDL compiler to be used for syntax analysis. |
vhdl-compiler-alist | List of available VHDL compilers and their properties. |
vhdl-components-package-name | Specifies how the name for the components package is obtained. |
vhdl-compose-architecture-name | Specifies how the component architecture name is obtained. |
vhdl-compose-configuration-create-file | Specifies whether a new file should be created for the configuration. |
vhdl-compose-configuration-hierarchical | Specifies whether hierarchical configurations should be created. |
vhdl-compose-configuration-name | Specifies how the configuration name is obtained. |
vhdl-compose-configuration-use-subconfiguration | Specifies whether subconfigurations should be used inside configurations. |
vhdl-compose-create-files | Specifies whether new files should be created for the new component. |
vhdl-compose-include-header | Non-nil means include a header in automatically generated files. |
vhdl-conditions-in-parenthesis | Non-nil means place parenthesis around condition expressions. |
vhdl-config-alist | Cache with configurations for each project/directory. |
vhdl-configuration-file-name | Specifies how the configuration file name is obtained. |
vhdl-constants | List of VHDL standardized constants. |
vhdl-constants-regexp | Regexp for VHDL standardized constants. |
vhdl-copyright-string | Copyright string to insert in file header. |
vhdl-date-format | Specifies the date format to use in the header. |
vhdl-default-library | Name of default library. |
vhdl-directive-keywords | List of compiler directive keywords recognized for highlighting. |
vhdl-directives | List of VHDL standardized packages and libraries. |
vhdl-directory-alist | Cache with source directories for each project. |
vhdl-doc-coding-style | For VHDL coding style and naming convention guidelines, see the following |
vhdl-doc-keywords | Reserved words in VHDL |
vhdl-doc-release-notes | Release Notes for VHDL Mode 3.37 |
vhdl-echo-syntactic-information-p | If non-nil, syntactic info is echoed when the line is indented. |
vhdl-electric-keywords | Type of keywords for which electrification is enabled. |
vhdl-electric-mode | Non-nil if Vhdl-Electric mode is enabled. |
vhdl-electric-mode-hook | Hook run after entering or leaving ‘vhdl-electric-mode’. |
vhdl-emacs-22 | Non-nil if GNU Emacs >= 22, ... is used. |
vhdl-end-comment-column | End of comment column. |
vhdl-ent-inst-alist | Cache with instantiated entities for each project/directory. |
vhdl-entity-alist | Cache with entities and corresponding architectures for each project/directory. |
vhdl-entity-file-name | Specifies how the entity file name is obtained. |
vhdl-enum-values | List of VHDL standardized enumeration values. |
vhdl-enum-values-regexp | Regexp for VHDL standardized enumeration values. |
vhdl-error-regexp-emacs-alist | List of regexps for VHDL compilers. For Emacs 22+. |
vhdl-file-alist | Cache with design units in each file for each project/directory. |
vhdl-file-footer | String or file to insert as file footer. |
vhdl-file-header | String or file to insert as file header. |
vhdl-file-name-case | Specifies how to change case for obtaining file names. |
vhdl-font-lock-attribute-face | Face name to use for standardized attributes. |
vhdl-font-lock-directive-face | Face name to use for directives. |
vhdl-font-lock-enumvalue-face | Face name to use for standardized enumeration values. |
vhdl-font-lock-function-face | Face name to use for standardized functions and packages. |
vhdl-font-lock-generic-/constant-face | Face name to use for generic/constant. |
vhdl-font-lock-keywords | Regular expressions to highlight in VHDL Mode. |
vhdl-font-lock-keywords-0 | For consideration as a value of ‘vhdl-font-lock-keywords’. |
vhdl-font-lock-keywords-1 | For consideration as a value of ‘vhdl-font-lock-keywords’. |
vhdl-font-lock-keywords-2 | For consideration as a value of ‘vhdl-font-lock-keywords’. |
vhdl-font-lock-keywords-3 | For consideration as a value of ‘vhdl-font-lock-keywords’. |
vhdl-font-lock-keywords-4 | For consideration as a value of ‘vhdl-font-lock-keywords’. |
vhdl-font-lock-keywords-5 | For consideration as a value of ‘vhdl-font-lock-keywords’. |
vhdl-font-lock-prompt-face | Face name to use for prompts. |
vhdl-font-lock-reserved-words-face | Face name to use for additional reserved words. |
vhdl-font-lock-syntactic-keywords | Mark single quotes as having string quote syntax in ‘c’ instances. |
vhdl-font-lock-translate-off-face | Face name to use for translate-off regions. |
vhdl-font-lock-type-face | Face name to use for type. |
vhdl-font-lock-variable-face | Face name to use for variable. |
vhdl-forbidden-syntax | Syntax of forbidden words to be highlighted. |
vhdl-forbidden-words | List of forbidden words to be highlighted. |
vhdl-functions | List of VHDL standardized functions. |
vhdl-functions-regexp | Regexp for VHDL standardized functions. |
vhdl-hide-all-init | Non-nil means hide all design units initially after a file is loaded. |
vhdl-hideshow-menu | Non-nil means add hideshow menu and functionality at startup. |
vhdl-highlight-case-sensitive | Non-nil means consider case for highlighting. |
vhdl-highlight-forbidden-words | Non-nil means highlight forbidden words. |
vhdl-highlight-keywords | Non-nil means highlight VHDL keywords and other standardized words. |
vhdl-highlight-names | Non-nil means highlight declaration names and construct labels. |
vhdl-highlight-special-words | Non-nil means highlight words with special syntax. |
vhdl-highlight-translate-off | Non-nil means background-highlight code excluded from translation. |
vhdl-highlight-verilog-keywords | Non-nil means highlight Verilog keywords as reserved words. |
vhdl-hs-start-regexp | Regexp to match start of construct to hide. |
vhdl-imenu-generic-expression | Imenu generic expression for VHDL Mode. See ‘imenu-generic-expression’. |
vhdl-include-direction-comments | Non-nil means include port direction in instantiations as comments. |
vhdl-include-group-comments | Specifies whether to include group comments and spacings. |
vhdl-include-port-comments | Non-nil means include port comments when a port is pasted. |
vhdl-include-type-comments | Non-nil means include generic/port type in instantiations as comments. |
vhdl-indent-comment-like-next-code-line | Non-nil means comment lines are indented like the following code line. |
vhdl-indent-syntax-based | Non-nil means indent lines of code based on their syntactic context. |
vhdl-indent-tabs-mode | Non-nil means indentation can insert tabs. |
vhdl-index-menu | Non-nil means add an index menu for a source file when loading. |
vhdl-inhibit-startup-warnings-p | If non-nil, inhibits start up compatibility warnings. |
vhdl-inline-comment-column | Column to indent and align inline comments to. |
vhdl-insert-empty-lines | Specifies whether to insert empty lines in some templates. |
vhdl-instance-name | Specifies how an instance name is obtained. |
vhdl-intelligent-tab | Non-nil means ‘TAB’ does indentation, word completion and tab insertion. |
vhdl-keywords | List of VHDL keywords. |
vhdl-keywords-regexp | Regexp for VHDL keywords. |
vhdl-label-key | Regexp describing a VHDL label. |
vhdl-last-input-event | Last input event. |
vhdl-make-target | Default target for ‘vhdl-make’ command. |
vhdl-makefile-default-targets | List of default target names in Makefiles. |
vhdl-makefile-generation-hook | Functions to run at the end of Makefile generation. |
vhdl-math-constants | List of Math Packages standardized constants. |
vhdl-math-functions | List of Math Packages standardized functions. |
vhdl-math-packages | List of Math Packages standardized packages and libraries. |
vhdl-math-types | List of Math Packages standardized types. |
vhdl-menu-max-size | Specifies the maximum size of a menu before splitting it into submenus. |
vhdl-minibuffer-local-map | Keymap for minibuffer used in VHDL Mode. |
vhdl-mode-abbrev-table | Abbrev table to use in ‘vhdl-mode’ buffers. |
vhdl-mode-ext-syntax-table | Syntax table extended by ‘_’ used in ‘vhdl-mode’ buffers. |
vhdl-mode-help-address | Address for VHDL Mode bug reports. |
vhdl-mode-hook | Hook called by ‘vhdl-mode’. |
vhdl-mode-map | Keymap for VHDL Mode. |
vhdl-mode-menu-list | VHDL Mode menu. |
vhdl-mode-syntax-table | Syntax table used in ‘vhdl-mode’ buffers. |
vhdl-model-alist | List of user models. |
vhdl-model-map | Keymap for VHDL models. |
vhdl-modified-file-list | List of modified files to be rescanned for hierarchy updating. |
vhdl-modify-date-on-saving | Non-nil means update the modification date when the buffer is saved. |
vhdl-modify-date-prefix-string | Prefix string of modification date in VHDL file header. |
vhdl-offsets-alist | Association list of syntactic element symbols and indentation offsets. |
vhdl-offsets-alist-default | Default settings for offsets of syntactic elements. |
vhdl-one-string | String to use for a logic one. |
vhdl-optional-labels | Constructs for which labels are to be queried. |
vhdl-package-alist | Cache with packages for each project/directory. |
vhdl-package-file-name | Specifies how the package file name is obtained. |
vhdl-packages | List of VHDL standardized packages and libraries. |
vhdl-packages-regexp | Regexp for VHDL standardized packages and libraries. |
vhdl-platform-spec | Specification of VHDL platform to insert in file header. |
vhdl-port-flattened | Indicates whether a port has been flattened. |
vhdl-port-list | Variable to hold last port map parsed. |
vhdl-port-reversed-direction | Indicates whether port directions are reversed. |
vhdl-print-customize-faces | Non-nil means use an optimized set of faces for PostScript printing. |
vhdl-print-two-column | Non-nil means print code in two columns and landscape format. |
vhdl-progress-interval | Interval used to update progress status during long operations. |
vhdl-project | Specifies the default for the current project. |
vhdl-project-alist | List of projects and their properties. |
vhdl-project-auto-load | Automatically load project setups from files. |
vhdl-project-autoload | Automatically load project setups from files. |
vhdl-project-file-name | List of file names/paths for importing/exporting project setups. |
vhdl-project-sort | Non-nil means projects are displayed in alphabetical order. |
vhdl-prompt-for-comments | Non-nil means various templates prompt for user definable comments. |
vhdl-reserved-words | List of additional reserved words. |
vhdl-reserved-words-regexp | Regexp for additional reserved words. |
vhdl-reset-active-high | Non-nil means reset in sequential processes is active high. |
vhdl-reset-kind | Specifies which kind of reset to use in sequential processes. |
vhdl-reset-name | Name of reset signal to use in templates. |
vhdl-self-insert-comments | Non-nil means various templates automatically insert help comments. |
vhdl-sensitivity-list-all | Non-nil means use ‘all’ keyword in sensitivity list. |
vhdl-source-file-menu | Non-nil means add a menu of all source files in current directory. |
vhdl-special-indent-hook | Hook for user defined special indentation adjustments. |
vhdl-special-syntax-alist | List of special syntax to be highlighted. |
vhdl-speedbar-auto-open | Non-nil means automatically open speedbar at startup. |
vhdl-speedbar-cache-file-name | Name of file for saving hierarchy cache. |
vhdl-speedbar-display-mode | Specifies the default displaying mode when opening speedbar. |
vhdl-speedbar-hierarchy-depth | Depth of instantiation hierarchy to display. |
vhdl-speedbar-jump-to-unit | Non-nil means jump to the design unit code when opened in a buffer. |
vhdl-speedbar-last-selected-project | Name of last selected project. |
vhdl-speedbar-menu-items | Additional menu-items to add to speedbar frame. |
vhdl-speedbar-mode-map | Keymap used when in the VHDL hierarchy browser mode. |
vhdl-speedbar-save-cache | Automatically save modified hierarchy caches when exiting Emacs. |
vhdl-speedbar-scan-limit | Limits scanning of large files and netlists. |
vhdl-speedbar-show-projects | Non-nil means project hierarchy is displayed in speedbar, directory |
vhdl-speedbar-shown-project-list | List of projects simultaneously open in the current speedbar. |
vhdl-speedbar-shown-unit-alist | Alist of design units simultaneously open in the current speedbar for each |
vhdl-speedbar-update-current-unit | Non-nil means to run ‘vhdl-speedbar-update-current-unit’. |
vhdl-speedbar-update-on-saving | Automatically update design hierarchy when buffer is saved. |
vhdl-standard | VHDL standards used. |
vhdl-statement-bwd-re | Regexp for searching backward that matches all known "statement" keywords. |
vhdl-statement-fwd-re | Regexp for searching forward that matches all known "statement" keywords. |
vhdl-strict-syntax-p | If non-nil, all syntactic symbols must be found in ‘vhdl-offsets-alist’. |
vhdl-stutter-mode | Non-nil if Vhdl-Stutter mode is enabled. |
vhdl-stutter-mode-hook | Hook run after entering or leaving ‘vhdl-stutter-mode’. |
vhdl-style-alist | Styles of Indentation. |
vhdl-subprog-flattened | Indicates whether an subprogram interface has been flattened. |
vhdl-subprog-list | Variable to hold last subprogram interface parsed. |
vhdl-symbol-key | Regexp describing a VHDL symbol. |
vhdl-syntactic-context | Buffer local variable containing syntactic analysis list. |
vhdl-template-construct-alist | List of built-in construct templates. |
vhdl-template-directive-alist | List of built-in directive templates. |
vhdl-template-invoked-by-hook | Indicates whether a template has been invoked by a hook or by key or menu. |
vhdl-template-map | Keymap for VHDL templates. |
vhdl-template-package-alist | List of built-in package templates. |
vhdl-template-prompt-syntax | Syntax of prompt inserted by template generators. |
vhdl-testbench-architecture-file-name | Specifies how the testbench architecture file name is obtained. |
vhdl-testbench-architecture-name | Specifies how the testbench architecture name is obtained. |
vhdl-testbench-configuration-name | Specifies how the testbench configuration name is obtained. |
vhdl-testbench-create-files | Specifies whether new files should be created for the testbench. |
vhdl-testbench-declarations | String or file to be inserted in the testbench declarative part. |
vhdl-testbench-dut-name | Specifies how a DUT instance name is obtained. |
vhdl-testbench-entity-file-name | Specifies how the testbench entity file name is obtained. |
vhdl-testbench-entity-name | Specifies how the testbench entity name is obtained. |
vhdl-testbench-include-configuration | Non-nil means a testbench configuration is attached at the end. |
vhdl-testbench-include-header | Non-nil means include a header in automatically generated files. |
vhdl-testbench-include-library | Non-nil means a library/use clause for std_logic_1164 is included. |
vhdl-testbench-initialize-signals | Non-nil means initialize signals with ‘0’ when declared in testbench. |
vhdl-testbench-statements | String or file to be inserted in the testbench statement part. |
vhdl-time-stamp | VHDL Mode time stamp for last update. |
vhdl-types | List of VHDL standardized types. |
vhdl-types-regexp | Regexp for VHDL standardized types. |
vhdl-underscore-is-part-of-word | Non-nil means consider the underscore character ‘_’ as part of word. |
vhdl-updated-project-list | List of projects and directories with updated files. |
vhdl-upper-case-attributes | Non-nil means convert standardized attributes to upper case. |
vhdl-upper-case-constants | Non-nil means convert standardized constants to upper case. |
vhdl-upper-case-enum-values | Non-nil means convert standardized enumeration values to upper case. |
vhdl-upper-case-keywords | Non-nil means convert keywords to upper case. |
vhdl-upper-case-types | Non-nil means convert standardized types to upper case. |
vhdl-use-components-package | Non-nil means use a separate components package for component declarations. |
vhdl-use-direct-instantiation | Non-nil means use VHDL’93 direct component instantiation. |
vhdl-verilog-keywords | List of Verilog keywords as candidate for additional reserved words. |
vhdl-version | VHDL Mode version number. |
vhdl-warnings | Warnings to tell the user during start up. |
vhdl-word-completion-case-sensitive | Non-nil means word completion using ‘TAB’ is case sensitive. |
vhdl-word-completion-in-minibuffer | Non-nil enables word completion in minibuffer (for template prompts). |
vhdl-zero-string | String to use for a logic zero. |
Defined functions (476)
Defined faces (22)
vhdl-font-lock-attribute-face | Font lock mode face used to highlight standardized attributes. |
vhdl-font-lock-directive-face | Font lock mode face used to highlight directives. |
vhdl-font-lock-enumvalue-face | Font lock mode face used to highlight standardized enumeration values. |
vhdl-font-lock-function-face | Font lock mode face used to highlight standardized functions and packages. |
vhdl-font-lock-generic-/constant-face | Font lock mode face used to highlight generic/constant. |
vhdl-font-lock-prompt-face | Font lock mode face used to highlight prompts. |
vhdl-font-lock-reserved-words-face | Font lock mode face used to highlight additional reserved words. |
vhdl-font-lock-translate-off-face | Font lock mode face used to background highlight translate-off regions. |
vhdl-font-lock-type-face | Font lock mode face used to highlight type. |
vhdl-font-lock-variable-face | Font lock mode face used to highlight variable. |
vhdl-speedbar-architecture-face | Face used for displaying architecture names. |
vhdl-speedbar-architecture-selected-face | Face used for displaying architecture names. |
vhdl-speedbar-configuration-face | Face used for displaying configuration names. |
vhdl-speedbar-configuration-selected-face | Face used for displaying configuration names. |
vhdl-speedbar-entity-face | Face used for displaying entity names. |
vhdl-speedbar-entity-selected-face | Face used for displaying entity names. |
vhdl-speedbar-instantiation-face | Face used for displaying instantiation names. |
vhdl-speedbar-instantiation-selected-face | Face used for displaying instantiation names. |
vhdl-speedbar-library-face | Face used for displaying library names. |
vhdl-speedbar-package-face | Face used for displaying package names. |
vhdl-speedbar-package-selected-face | Face used for displaying package names. |
vhdl-speedbar-subprogram-face | Face used for displaying subprogram names. |