Variable: verilog-auto-inst-vector

verilog-auto-inst-vector is a customizable variable defined in verilog-mode.el.gz.

Value

t

Documentation

Non-nil means when creating default ports with AUTOINST, use bus subscripts.

If nil, skip the subscript when it matches the entire bus as declared in the module (AUTOWIRE signals always are subscripted, you must manually
declare the wire to have the subscripts removed.) Setting this to nil may
speed up some simulators, but is less general and harder to read, so avoid. If unsigned, use vectors for unsigned types (like using true, otherwise no vectors if sizes match (like using nil).

Source Code

;; Defined in /usr/src/emacs/lisp/progmodes/verilog-mode.el.gz
(defcustom verilog-auto-inst-vector t
  "Non-nil means when creating default ports with AUTOINST, use bus subscripts.
If nil, skip the subscript when it matches the entire bus as declared in
the module (AUTOWIRE signals always are subscripted, you must manually
declare the wire to have the subscripts removed.)  Setting this to nil may
speed up some simulators, but is less general and harder to read, so avoid.
If `unsigned', use vectors for unsigned types (like using true,
otherwise no vectors if sizes match (like using nil)."
  :group 'verilog-mode-auto
  :type '(choice (const nil) (const t) (const unsigned)))