Variable: verilog-compiler-directives

verilog-compiler-directives is a variable defined in verilog-mode.el.gz.

Value

("`__FILE__" "`__LINE" "`begin_keywords" "`celldefine"
 "`default_nettype" "`define" "`else" "`elsif" "`end_keywords"
 "`endcelldefine" "`endif" "`ifdef" "`ifndef" "`include" "`line"
 "`nounconnected_drive" "`pragma" "`resetall" "`timescale"
 "`unconnected_drive" "`undef" "`undefineall" "`case" "`default"
 "`endfor" "`endprotect" "`endswitch" "`endwhile" "`for" "`format"
 "`if" "`let" "`protect" "`switch" "`time_scale" "`uselib" "`while")

Documentation

List of Verilog compiler directives.

Source Code

;; Defined in /usr/src/emacs/lisp/progmodes/verilog-mode.el.gz
(defconst verilog-compiler-directives
  (eval-when-compile
    '(
      ;; compiler directives, from IEEE 1800-2012 section 22.1
      "`__FILE__" "`__LINE" "`begin_keywords" "`celldefine" "`default_nettype"
      "`define" "`else" "`elsif" "`end_keywords" "`endcelldefine" "`endif"
      "`ifdef" "`ifndef" "`include" "`line" "`nounconnected_drive" "`pragma"
      "`resetall" "`timescale" "`unconnected_drive" "`undef" "`undefineall"
      ;; compiler directives not covered by IEEE 1800
      "`case" "`default" "`endfor" "`endprotect" "`endswitch" "`endwhile" "`for"
      "`format" "`if" "`let" "`protect" "`switch" "`time_scale" "`uselib"
      "`while"
      ))
  "List of Verilog compiler directives.")