Variable: verilog-indent-level-module

verilog-indent-level-module is a customizable variable defined in verilog-mode.el.gz.

Value

3

Documentation

Indentation of Module level Verilog statements (eg always, initial).

Set to 0 to get initial and always statements lined up on the left side of your screen.

Source Code

;; Defined in /usr/src/emacs/lisp/progmodes/verilog-mode.el.gz
(defcustom verilog-indent-level-module 3
  "Indentation of Module level Verilog statements (eg always, initial).
Set to 0 to get initial and always statements lined up on the left side of
your screen."
  :group 'verilog-mode-indent
  :type 'integer)