Function: verilog-mode
verilog-mode is an autoloaded, interactive and byte-compiled function
defined in verilog-mode.el.gz.
Signature
(verilog-mode)
Documentation
Major mode for editing Verilog code.
See C-h f (describe-function) verilog-auto (C-c C-a (verilog-auto)) for details on how
AUTOs can improve coding efficiency.
Use M-x verilog-faq (verilog-faq) for a pointer to frequently asked questions.
NEWLINE, TAB indents for Verilog code. Delete converts tabs to spaces as it moves back.
Supports highlighting.
Turning on Verilog mode calls the value of the variable verilog-mode-hook
with no args, if that value is non-nil.
Variables controlling indentation/edit style:
variable verilog-indent-level (default 3)
Indentation of Verilog statements with respect to containing block.
verilog-indent-level-module (default 3)
Absolute indentation of Module level Verilog statements.
Set to 0 to get initial and always statements lined up
on the left side of your screen.
verilog-indent-level-declaration (default 3)
Indentation of declarations with respect to containing block.
Set to 0 to get them list right under containing block.
verilog-indent-level-behavioral (default 3)
Indentation of first begin in a task or function block
Set to 0 to get such code to lined up underneath the task or
function keyword.
verilog-indent-level-directive (default 1)
Indentation of `ifdef/`endif blocks.
verilog-indent-ignore-multiline-defines (default t)
Non-nil means ignore indentation on lines that are part of a multiline
define.
verilog-indent-ignore-regexp (default nil
Regexp that matches lines that should be ignored for indentation.
verilog-cexp-indent (default 1)
Indentation of Verilog statements broken across lines i.e.:
if (a)
begin
verilog-case-indent (default 2)
Indentation for case statements.
verilog-auto-newline (default nil)
Non-nil means automatically newline after semicolons and the punctuation
mark after an end.
verilog-auto-indent-on-newline (default t)
Non-nil means automatically indent line after newline.
verilog-tab-always-indent (default t)
Non-nil means TAB in Verilog mode should always reindent the current line,
regardless of where in the line point is when the TAB command is used.
verilog-indent-begin-after-if (default t)
Non-nil means to indent begin statements following a preceding
if, else, while, for and repeat statements, if any. Otherwise,
the begin is lined up with the preceding token. If t, you get:
if (a)
begin // amount of indent based on verilog-cexp-indent
otherwise you get:
if (a)
begin
verilog-indent-class-inside-pkg (default t)
Non-nil means indent classes inside packages.
Otherwise, classes have zero indentation.
verilog-auto-endcomments (default t)
Non-nil means a comment /* ... */ is set after the ends which ends
cases, tasks, functions and modules.
The type and name of the object will be set between the braces.
verilog-minimum-comment-distance (default 10)
Minimum distance (in lines) between begin and end required before a comment
will be inserted. Setting this variable to zero results in every
end acquiring a comment; the default avoids too many redundant
comments in tight quarters.
verilog-align-decl-expr-comments (default t)
Non-nil means align declaration and expressions comments.
verilog-align-comment-distance (default 1)
Distance (in spaces) between longest declaration and comments.
Only works if verilog-align-decl-expr-comments is non-nil.
verilog-align-assign-expr (default nil)
Non-nil means align expressions of continuous assignments.
verilog-align-typedef-regexp (default nil)
Regexp that matches user typedefs for declaration alignment.
verilog-align-typedef-words (default nil)
List of words that match user typedefs for declaration alignment.
verilog-auto-lineup (default declarations)
List of contexts where auto lineup of code should be done.
Variables controlling other actions:
verilog-linter (default none)
Unix program to call to run the lint checker. This is the default
command for M-x compile-command (compile-command) and C-c C-s (verilog-auto-save-compile).
See M-x customize (customize) for the complete list of variables.
AUTO expansion functions are, in part:
C-c C-a (verilog-auto) Expand AUTO statements.
C-c C-k (verilog-delete-auto) Remove the AUTOs.
C-c C-z (verilog-inject-auto) Insert AUTOs for the first time.
Some other functions are:
C-M-i (completion-at-point) Complete word with appropriate possibilities.
C-M-h (verilog-mark-defun) Mark function.
C-M-a (verilog-beg-of-defun) Move to beginning of current function.
C-M-e (verilog-end-of-defun) Move to end of current function.
C-c C-r (verilog-label-be) Label matching begin ... end, fork ... join, etc
statements.
C-c C-c (verilog-comment-region) Put marked area in a comment.
C-c C-u (verilog-uncomment-region) Uncomment an area commented with
C-c C-c (verilog-comment-region).
M-x verilog-insert-block (verilog-insert-block) Insert begin ... end.
C-c / (verilog-star-comment) Insert /* ... */.
C-c C-t a (verilog-sk-always) Insert an always @(AS) begin .. end block.
C-c C-t b (verilog-sk-begin) Insert a begin .. end block.
C-c C-t c (verilog-sk-case) Insert a case block, prompting for details.
C-c C-t f (verilog-sk-for) Insert a for (...) begin .. end block, prompting for
details.
C-c C-t g (verilog-sk-generate) Insert a generate .. endgenerate block.
C-c C-t h (verilog-sk-header) Insert a header block at the top of file.
C-c C-t i (verilog-sk-initial) Insert an initial begin .. end block.
C-c C-t j (verilog-sk-fork) Insert a fork begin .. end .. join block.
C-c C-t m (verilog-sk-module) Insert a module .. (/*AUTOARG*/);.. endmodule block.
C-c C-t o (verilog-sk-ovm-class) Insert an OVM Class block.
C-c C-t u (verilog-sk-uvm-object) Insert an UVM Object block.
C-c C-t U (verilog-sk-uvm-component) Insert an UVM Component block.
C-c C-t p (verilog-sk-primitive) Insert a primitive .. (.. );.. endprimitive block.
C-c C-t r (verilog-sk-repeat) Insert a repeat (..) begin .. end block.
C-c C-t s (verilog-sk-specify) Insert a specify .. endspecify block.
C-c C-t t (verilog-sk-task) Insert a task .. begin .. end endtask block.
C-c C-t w (verilog-sk-while) Insert a while (...) begin .. end block,
prompting for details.
C-c C-t x (verilog-sk-casex) Insert a casex (...) item: begin.. end endcase block,
prompting for details.
C-c C-t z (verilog-sk-casez) Insert a casez (...) item: begin.. end endcase block,
prompting for details.
C-c C-t ? (verilog-sk-if) Insert an if (..) begin .. end block.
C-c C-t : (verilog-sk-else-if) Insert an else if (..) begin .. end block.
C-c C-t / (verilog-sk-comment) Insert a comment block.
C-c C-t A (verilog-sk-assign) Insert an assign .. = ..; statement.
C-c C-t F (verilog-sk-function) Insert a function .. begin .. end endfunction
block.
C-c C-t I (verilog-sk-input) Insert an input declaration, prompting for details.
C-c C-t O (verilog-sk-output) Insert an output declaration, prompting for details.
C-c C-t S (verilog-sk-state-machine) Insert a state machine definition, prompting
for details.
C-c C-t = (verilog-sk-inout) Insert an inout declaration, prompting for details.
C-c C-t W (verilog-sk-wire) Insert a wire declaration, prompting for details.
C-c C-t R (verilog-sk-reg) Insert a register declaration, prompting for details.
C-c C-t D (verilog-sk-define-signal) Define signal under point as a register at
the top of the module.
All key bindings can be seen in a Verilog-buffer with C-h b (describe-bindings).
Key bindings specific to verilog-mode-map are:
: electric-verilog-colon
; electric-verilog-semi
<backspace> backward-delete-char-untabify
<delete> delete-char
C-; electric-verilog-semi-with-comment
C-M-a verilog-beg-of-defun
C-M-b electric-verilog-backward-sexp
C-M-e verilog-end-of-defun
C-M-f electric-verilog-forward-sexp
C-M-h verilog-mark-defun
C-M-i completion-at-point
C-c * verilog-delete-auto-star-implicit
C-c / verilog-star-comment
C-c = verilog-pretty-expr
C-c ? verilog-diff-auto
C-c C-a verilog-auto
C-c C-c verilog-comment-region
C-c C-d verilog-goto-defun
C-c C-e verilog-expand-vector
C-c C-h verilog-header
C-c C-k verilog-delete-auto
C-c C-p verilog-preprocess
C-c C-r verilog-label-be
C-c C-s verilog-auto-save-compile
C-c C-t / verilog-sk-comment
C-c C-t : verilog-sk-else-if
C-c C-t = verilog-sk-inout
C-c C-t ? verilog-sk-if
C-c C-t A verilog-sk-assign
C-c C-t D verilog-sk-define-signal
C-c C-t F verilog-sk-function
C-c C-t I verilog-sk-input
C-c C-t O verilog-sk-output
C-c C-t R verilog-sk-reg
C-c C-t S verilog-sk-state-machine
C-c C-t U verilog-sk-uvm-component
C-c C-t W verilog-sk-wire
C-c C-t a verilog-sk-always
C-c C-t b verilog-sk-begin
C-c C-t c verilog-sk-case
C-c C-t f verilog-sk-for
C-c C-t g verilog-sk-generate
C-c C-t h verilog-sk-header
C-c C-t i verilog-sk-initial
C-c C-t j verilog-sk-fork
C-c C-t m verilog-sk-module
C-c C-t o verilog-sk-ovm-class
C-c C-t p verilog-sk-primitive
C-c C-t r verilog-sk-repeat
C-c C-t s verilog-sk-specify
C-c C-t t verilog-sk-task
C-c C-t u verilog-sk-uvm-object
C-c C-t w verilog-sk-while
C-c C-t x verilog-sk-casex
C-c C-t z verilog-sk-casez
C-c C-u verilog-uncomment-region
C-c C-z verilog-inject-auto
C-c TAB verilog-pretty-declarations
C-c ` verilog-lint-off
M-<delete> kill-word
M-? completion-help-at-point
M-RET electric-verilog-terminate-and-indent
RET electric-verilog-terminate-line
TAB electric-verilog-tab
` electric-verilog-tick
Probably introduced at or before Emacs version 22.2.
Key Bindings
Source Code
;; Defined in /usr/src/emacs/lisp/progmodes/verilog-mode.el.gz
;;;###autoload
(define-derived-mode verilog-mode prog-mode "Verilog"
"Major mode for editing Verilog code.
\\<verilog-mode-map>
See \\[describe-function] verilog-auto (\\[verilog-auto]) for details on how
AUTOs can improve coding efficiency.
Use \\[verilog-faq] for a pointer to frequently asked questions.
NEWLINE, TAB indents for Verilog code.
Delete converts tabs to spaces as it moves back.
Supports highlighting.
Turning on Verilog mode calls the value of the variable `verilog-mode-hook'
with no args, if that value is non-nil.
Variables controlling indentation/edit style:
variable `verilog-indent-level' (default 3)
Indentation of Verilog statements with respect to containing block.
`verilog-indent-level-module' (default 3)
Absolute indentation of Module level Verilog statements.
Set to 0 to get initial and always statements lined up
on the left side of your screen.
`verilog-indent-level-declaration' (default 3)
Indentation of declarations with respect to containing block.
Set to 0 to get them list right under containing block.
`verilog-indent-level-behavioral' (default 3)
Indentation of first begin in a task or function block
Set to 0 to get such code to lined up underneath the task or
function keyword.
`verilog-indent-level-directive' (default 1)
Indentation of \\=`ifdef/\\=`endif blocks.
`verilog-indent-ignore-multiline-defines' (default t)
Non-nil means ignore indentation on lines that are part of a multiline
define.
`verilog-indent-ignore-regexp' (default nil
Regexp that matches lines that should be ignored for indentation.
`verilog-cexp-indent' (default 1)
Indentation of Verilog statements broken across lines i.e.:
if (a)
begin
`verilog-case-indent' (default 2)
Indentation for case statements.
`verilog-auto-newline' (default nil)
Non-nil means automatically newline after semicolons and the punctuation
mark after an end.
`verilog-auto-indent-on-newline' (default t)
Non-nil means automatically indent line after newline.
`verilog-tab-always-indent' (default t)
Non-nil means TAB in Verilog mode should always reindent the current line,
regardless of where in the line point is when the TAB command is used.
`verilog-indent-begin-after-if' (default t)
Non-nil means to indent begin statements following a preceding
if, else, while, for and repeat statements, if any. Otherwise,
the begin is lined up with the preceding token. If t, you get:
if (a)
begin // amount of indent based on `verilog-cexp-indent'
otherwise you get:
if (a)
begin
`verilog-indent-class-inside-pkg' (default t)
Non-nil means indent classes inside packages.
Otherwise, classes have zero indentation.
`verilog-auto-endcomments' (default t)
Non-nil means a comment /* ... */ is set after the ends which ends
cases, tasks, functions and modules.
The type and name of the object will be set between the braces.
`verilog-minimum-comment-distance' (default 10)
Minimum distance (in lines) between begin and end required before a comment
will be inserted. Setting this variable to zero results in every
end acquiring a comment; the default avoids too many redundant
comments in tight quarters.
`verilog-align-decl-expr-comments' (default t)
Non-nil means align declaration and expressions comments.
`verilog-align-comment-distance' (default 1)
Distance (in spaces) between longest declaration and comments.
Only works if `verilog-align-decl-expr-comments' is non-nil.
`verilog-align-assign-expr' (default nil)
Non-nil means align expressions of continuous assignments.
`verilog-align-typedef-regexp' (default nil)
Regexp that matches user typedefs for declaration alignment.
`verilog-align-typedef-words' (default nil)
List of words that match user typedefs for declaration alignment.
`verilog-auto-lineup' (default `declarations')
List of contexts where auto lineup of code should be done.
Variables controlling other actions:
`verilog-linter' (default `none')
Unix program to call to run the lint checker. This is the default
command for \\[compile-command] and \\[verilog-auto-save-compile].
See \\[customize] for the complete list of variables.
AUTO expansion functions are, in part:
\\[verilog-auto] Expand AUTO statements.
\\[verilog-delete-auto] Remove the AUTOs.
\\[verilog-inject-auto] Insert AUTOs for the first time.
Some other functions are:
\\[completion-at-point] Complete word with appropriate possibilities.
\\[verilog-mark-defun] Mark function.
\\[verilog-beg-of-defun] Move to beginning of current function.
\\[verilog-end-of-defun] Move to end of current function.
\\[verilog-label-be] Label matching begin ... end, fork ... join, etc
statements.
\\[verilog-comment-region] Put marked area in a comment.
\\[verilog-uncomment-region] Uncomment an area commented with
\\[verilog-comment-region].
\\[verilog-insert-block] Insert begin ... end.
\\[verilog-star-comment] Insert /* ... */.
\\[verilog-sk-always] Insert an always @(AS) begin .. end block.
\\[verilog-sk-begin] Insert a begin .. end block.
\\[verilog-sk-case] Insert a case block, prompting for details.
\\[verilog-sk-for] Insert a for (...) begin .. end block, prompting for
details.
\\[verilog-sk-generate] Insert a generate .. endgenerate block.
\\[verilog-sk-header] Insert a header block at the top of file.
\\[verilog-sk-initial] Insert an initial begin .. end block.
\\[verilog-sk-fork] Insert a fork begin .. end .. join block.
\\[verilog-sk-module] Insert a module .. (/*AUTOARG*/);.. endmodule block.
\\[verilog-sk-ovm-class] Insert an OVM Class block.
\\[verilog-sk-uvm-object] Insert an UVM Object block.
\\[verilog-sk-uvm-component] Insert an UVM Component block.
\\[verilog-sk-primitive] Insert a primitive .. (.. );.. endprimitive block.
\\[verilog-sk-repeat] Insert a repeat (..) begin .. end block.
\\[verilog-sk-specify] Insert a specify .. endspecify block.
\\[verilog-sk-task] Insert a task .. begin .. end endtask block.
\\[verilog-sk-while] Insert a while (...) begin .. end block,
prompting for details.
\\[verilog-sk-casex] Insert a casex (...) item: begin.. end endcase block,
prompting for details.
\\[verilog-sk-casez] Insert a casez (...) item: begin.. end endcase block,
prompting for details.
\\[verilog-sk-if] Insert an if (..) begin .. end block.
\\[verilog-sk-else-if] Insert an else if (..) begin .. end block.
\\[verilog-sk-comment] Insert a comment block.
\\[verilog-sk-assign] Insert an assign .. = ..; statement.
\\[verilog-sk-function] Insert a function .. begin .. end endfunction
block.
\\[verilog-sk-input] Insert an input declaration, prompting for details.
\\[verilog-sk-output] Insert an output declaration, prompting for details.
\\[verilog-sk-state-machine] Insert a state machine definition, prompting
for details.
\\[verilog-sk-inout] Insert an inout declaration, prompting for details.
\\[verilog-sk-wire] Insert a wire declaration, prompting for details.
\\[verilog-sk-reg] Insert a register declaration, prompting for details.
\\[verilog-sk-define-signal] Define signal under point as a register at
the top of the module.
All key bindings can be seen in a Verilog-buffer with \\[describe-bindings].
Key bindings specific to `verilog-mode-map' are:
\\{verilog-mode-map}"
:abbrev-table verilog-mode-abbrev-table
(set (make-local-variable 'beginning-of-defun-function)
#'verilog-beg-of-defun)
(set (make-local-variable 'end-of-defun-function)
#'verilog-end-of-defun)
(set-syntax-table verilog-mode-syntax-table)
(set (make-local-variable 'indent-line-function)
#'verilog-indent-line-relative)
(set (make-local-variable 'comment-indent-function) #'verilog-comment-indent)
(set (make-local-variable 'parse-sexp-ignore-comments) nil)
(set (make-local-variable 'comment-start) "// ")
(set (make-local-variable 'comment-end) "")
(set (make-local-variable 'comment-start-skip) "/\\*+ *\\|// *")
(set (make-local-variable 'comment-multi-line) nil)
;; Set up for compilation
(setq verilog-which-tool 1)
(setq verilog-tool 'verilog-linter)
(verilog-set-compile-command)
(when (boundp 'hack-local-variables-hook) ; Also modify any file-local-variables
(add-hook 'hack-local-variables-hook #'verilog-modify-compile-command t))
;; Setting up menus
(when (featurep 'xemacs)
(easy-menu-add verilog-stmt-menu)
(easy-menu-add verilog-menu)
(setq mode-popup-menu (cons "Verilog Mode" verilog-stmt-menu)))
;; Stuff for GNU Emacs
(set (make-local-variable 'font-lock-defaults)
`((verilog-font-lock-keywords
verilog-font-lock-keywords-1
verilog-font-lock-keywords-2
verilog-font-lock-keywords-3)
nil nil nil
,(if (functionp 'syntax-ppss)
;; verilog-beg-of-defun uses syntax-ppss, and syntax-ppss uses
;; font-lock-beginning-of-syntax-function, so
;; font-lock-beginning-of-syntax-function, can't use
;; verilog-beg-of-defun.
nil
'verilog-beg-of-defun)))
;; Stuff for multiline font-lock
(set (make-local-variable 'font-lock-multiline) t)
;;------------------------------------------------------------
;; now hook in 'verilog-highlight-include-files (eldo-mode.el&spice-mode.el)
;; all buffer local:
(unless noninteractive ; Else can't see the result, and change hooks are slow
(when (featurep 'xemacs)
(make-local-hook 'font-lock-mode-hook)
(make-local-hook 'font-lock-after-fontify-buffer-hook); doesn't exist in Emacs
(make-local-hook 'after-change-functions))
(add-hook 'font-lock-mode-hook #'verilog-highlight-buffer t t)
(add-hook 'font-lock-after-fontify-buffer-hook #'verilog-highlight-buffer t t) ; not in Emacs
(add-hook 'after-change-functions #'verilog-highlight-region t t))
;; Tell imenu how to handle Verilog.
(set (make-local-variable 'imenu-generic-expression)
verilog-imenu-generic-expression)
;; Tell which-func-modes that imenu knows about verilog
(when (and (boundp 'which-func-modes) (listp which-func-modes))
(add-to-list 'which-func-modes 'verilog-mode))
;; hideshow support
(cond ((boundp 'hs-forward-sexp-function) ;; 31.1 and beyond
(setq-local hs-block-start-regexp "\\<begin\\>")
(setq-local hs-block-end-regexp "\\<end\\>")
(setq-local hs-forward-sexp-function #'verilog-forward-sexp-function))
((boundp 'hs-special-modes-alist) ;; pre 31.1, not XEmacs
(unless (assq 'verilog-mode hs-special-modes-alist)
(setq hs-special-modes-alist
(cons '(verilog-mode "\\<begin\\>" "\\<end\\>" nil
verilog-forward-sexp-function)
hs-special-modes-alist)))))
(add-hook 'completion-at-point-functions
#'verilog-completion-at-point nil 'local)
;; Stuff for autos
(add-hook (if (boundp 'write-contents-hooks) 'write-contents-hooks
'write-contents-functions) ; Emacs >= 22.1
#'verilog-auto-save-check nil 'local)
;; verilog-mode-hook call added by define-derived-mode
)